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m68hc05 microcontrollers freescale.com mc68hc05jj6 mc68hc05jp6 general release specification hc05jj6grs/d rev. 3.2 01/2007

mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor list of sections 3 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 19 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 section 3. central processor unit (cpu) . . . . . . . . . . . . 39 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 section 6. operating modes. . . . . . . . . . . . . . . . . . . . . . 69 section 7. parallel input/output . . . . . . . . . . . . . . . . . . . 77 section 8. analog subsystem . . . . . . . . . . . . . . . . . . . . 103 section 9. simple serial interface . . . . . . . . . . . . . . . . 137 section 10. core timer . . . . . . . . . . . . . . . . . . . . . . . . . 147 section 11. programmable timer. . . . . . . . . . . . . . . . . 155 section 12. instruction set . . . . . . . . . . . . . . . . . . . . . . . 171 section 13. electrical specifications . . . . . . . . . . . . . . 189 section 14. mechanical specifications . . . . . . . . . . . . 207 section 15. ordering information . . . . . . . . . . . . . . . . . 211
non-disclosure agreement required list of sections general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 4 list of sections freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor table of contents 5 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6 v dd and v ss pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7 osc1 and osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.7.2 ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . . .27 1.7.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.5 internal low-power oscillator . . . . . . . . . . . . . . . . . . . . . . .28 1.8 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.9 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.10 pa0?a5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.11 pb0?b7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.12 pc0?c7 (mc68hc05jp6) . . . . . . . . . . . . . . . . . . . . . . . . . . .30 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.4 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.5 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
non-disclosure agreement required table of contents general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 6 table of contents freescale semiconductor 2.6 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.7 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8 rom security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.9 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.5 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.6 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.7 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.8 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .44 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.5 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.1 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.2 pa0?a3 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.6.3 irq status and control register. . . . . . . . . . . . . . . . . . . . .53 4.7 core timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.7.1 core timer overflow interrupt. . . . . . . . . . . . . . . . . . . . . . .55 4.7.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
table of contents mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor table of contents 7 non-disclosure agreement required 4.8 programmable timer interrupts . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.1 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.2 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.9 serial interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.10 analog interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.10.1 comparator input match interrupt . . . . . . . . . . . . . . . . . . . .58 4.10.2 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.4 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.2 computer operating properly (cop) reset . . . . . . . . . . . .62 5.5.3 low-voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.5.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6 reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.1 cpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.3 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.4 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.5 16-bit programmable timer . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.6 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.7 analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 external oscillator and internal low-power oscillator . . . .67 section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.3 oscillator source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
non-disclosure agreement required table of contents general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 8 table of contents freescale semiconductor 6.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.4.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.4.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4.4 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 7. parallel input/output 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.3.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.3.4 port a external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.3.5 port a logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.4.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.4 port b logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.5 pb0, pbi, pb2, and pb3 logic . . . . . . . . . . . . . . . . . . . . . .87 7.4.6 pb4/an4/tcmp/cmp1 logic . . . . . . . . . . . . . . . . . . . . . . .89 7.4.7 pb5/sdo logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.4.8 pb6/sdi logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.9 pb7/sck logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 port c (mc68hc05jp6 only). . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.3 port c pulldown devices. . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.4 port c logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6 port transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
table of contents mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor table of contents 9 non-disclosure agreement required section 8. analog subsystem 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.3 analog multiplex register . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.4 analog control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.5 analog status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.6 a/d conversion methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.7 voltage measurement methods . . . . . . . . . . . . . . . . . . . . . . .128 8.7.1 absolute voltage readings . . . . . . . . . . . . . . . . . . . . . . . .129 8.7.1.1 internal absolute reference. . . . . . . . . . . . . . . . . . . . . .129 8.7.1.2 external absolute reference . . . . . . . . . . . . . . . . . . . . .130 8.7.2 ratiometric voltage readings. . . . . . . . . . . . . . . . . . . . . .131 8.7.2.1 internal ratiometric reference . . . . . . . . . . . . . . . . . . .131 8.7.2.2 external ratiometric reference . . . . . . . . . . . . . . . . . . .131 8.8 voltage comparator features . . . . . . . . . . . . . . . . . . . . . . . .133 8.9 current source features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.10 internal temperature sensing diode features. . . . . . . . . . . .134 8.11 sample and hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.12 port b interaction with analog inputs . . . . . . . . . . . . . . . . . . .135 8.13 port b pins as inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.14 port b pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.15 noise sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 section 9. simple serial interface 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9.3 siop signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.3.3 serial data output (sdo) . . . . . . . . . . . . . . . . . . . . . . . . .140
non-disclosure agreement required table of contents general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 10 table of contents freescale semiconductor 9.4 siop registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.1 siop control register . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 siop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.4.3 siop data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 section 10. core timer 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.3 core timer status and control register . . . . . . . . . . . . . . . .149 10.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . .151 10.5 cop watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 section 11. programmable timer 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 11.4 alternate counter registers . . . . . . . . . . . . . . . . . . . . . . . . .160 11.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 11.6 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . .164 11.7 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.8 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.9 timer operation during wait mode. . . . . . . . . . . . . . . . . . . . .169 11.10 timer operation during stop mode . . . . . . . . . . . . . . . . . . . .169 11.11 timer operation during halt mode . . . . . . . . . . . . . . . . . . . . .169 section 12. instruction set 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
table of contents mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor table of contents 11 non-disclosure agreement required 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .176 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .177 12.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .178 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 section 13. electrical specifications 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .191 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 13.6 supply current characteristics (v dd = 4.5 to 5.5 vdc). . . . . .192 13.7 supply current characteristics (v dd = 2.7 to 3.3 vdc). . . . . .193 13.8 dc electrical characteristics (5.0 vdc). . . . . . . . . . . . . . . . . .194 13.9 dc electrical characteristics (3.0 vdc). . . . . . . . . . . . . . . . . .195 13.10 analog subsystem characteristics (5.0 vdc) . . . . . . . . . . . . .198 13.11 analog subsystem characteristics (3.0 vdc) . . . . . . . . . . . . .199 13.12 control timing (5.0 vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.13 control timing (3.0 vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.14 siop timing (v dd = 5.0 vdc) . . . . . . . . . . . . . . . . . . . . . . . . .202
non-disclosure agreement required table of contents general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 12 table of contents freescale semiconductor 13.15 siop timing (v dd = 3.0 vdc) . . . . . . . . . . . . . . . . . . . . . . . . .203 13.16 reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 section 14. mechanical specifications 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.3 20-pin plastic dual in-line package (case 738) . . . . . . . . . .208 14.4 20-pin small outline integrated circuit (case 751d) . . . . . . .208 14.5 28-pin plastic dual in-line package (case 710) . . . . . . . . . .209 14.6 28-pin small outline integrated circuit (case 751f) . . . . . . .209 section 15. ordering information 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 15.3 mc68hc05jj6 order numbers . . . . . . . . . . . . . . . . . . . . . . .212 15.4 mc68hc05jp6 order numbers . . . . . . . . . . . . . . . . . . . . . . .212
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor list of figures 13 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 list of figures figure title page 1-1 user mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .23 1-2 user mode pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1-3 epo oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . .26 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2-2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2-3 i/o registers $0000?000f . . . . . . . . . . . . . . . . . . . . . . . . .34 2-4 i/o registers $0010?001f . . . . . . . . . . . . . . . . . . . . . . . . .35 2-5 vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2-6 rom security bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2-7 cop register (copr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3-1 68hc05 programming model . . . . . . . . . . . . . . . . . . . . . . . .40 3-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3-3 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . .42 4-1 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4-2 interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4-3 external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 4-4 irq status and control register (iscr) . . . . . . . . . . . . . . .53 5-1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5-2 cop register (copr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6-1 irq status and control register (iscr) . . . . . . . . . . . . . . .70 6-2 stop/wait/halt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .72
non-disclosure agreement required list of figures general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 14 list of figures freescale semiconductor figure title page 7-1 port a data register (porta). . . . . . . . . . . . . . . . . . . . . . .79 7-2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . .80 7-3 pulldown register a (pdra) . . . . . . . . . . . . . . . . . . . . . . . .81 7-4 port a i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7-5 port b data register (portb). . . . . . . . . . . . . . . . . . . . . . .84 7-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . .85 7-7 pulldown register b (pdrb) . . . . . . . . . . . . . . . . . . . . . . . .86 7-8 pb0:pb3 pin i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 7-9 pb4/an4/tcmp/cmp1 pin i/o circuit . . . . . . . . . . . . . . . . .89 7-10 pb5/sdo pin i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7-11 pb6/sdi pin i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7-12 pb7/sck pin i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7-13 port c data register (portc) . . . . . . . . . . . . . . . . . . . . . .99 7-14 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . .100 7-15 port c i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8-1 analog subsystem block diagram . . . . . . . . . . . . . . . . . . .104 8-2 analog multiplex register (amux) . . . . . . . . . . . . . . . . . . .106 8-3 comparator 2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . .107 8-4 inv bit action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 8-5 analog control register (acr) . . . . . . . . . . . . . . . . . . . . .111 8-6 analog status register (asr) . . . . . . . . . . . . . . . . . . . . . .115 8-7 single-slope a/d conversion method . . . . . . . . . . . . . . . .118 8-8 a/d conversion ?full manual control (mode 0) . . . . . . .124 8-9 a/d conversion ?manual/auto discharge control (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 8-10 a/d conversion ?tof/icf control (mode 2). . . . . . . . . .126 8-11 a/d conversion ?ocf/icf control (mode 3) . . . . . . . . .127 9-1 siop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 9-2 siop timing diagram (cpha = 0) . . . . . . . . . . . . . . . . . . .139 9-3 siop timing diagram (cpha = 1) . . . . . . . . . . . . . . . . . . .140 9-4 siop control register (scr) . . . . . . . . . . . . . . . . . . . . . . .141 9-5 siop status register (ssr) . . . . . . . . . . . . . . . . . . . . . . .144 9-6 siop data register (sdr) . . . . . . . . . . . . . . . . . . . . . . . . .145
list of figures mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor list of figures 15 non-disclosure agreement required figure title page 10-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . .148 10-2 core timer status and control register (ctscr) . . . . . .149 10-3 core timer counter register (ctcr) . . . . . . . . . . . . . . . .151 10-4 cop and security register (copr) . . . . . . . . . . . . . . . . .152 11-1 programmable timer overall block diagram . . . . . . . . . . .157 11-2 programmable timer block diagram . . . . . . . . . . . . . . . . .158 11-3 programmable timer registers (tmrh and tmrl) . . . . .159 11-4 alternate counter block diagram . . . . . . . . . . . . . . . . . . . .160 11-5 alternate counter registers (acrh and acrl) . . . . . . . .161 11-6 timer input capture block diagram . . . . . . . . . . . . . . . . . .162 11-7 input capture registers (icrh and icrl) . . . . . . . . . . . . .163 11-8 timer output compare block diagram . . . . . . . . . . . . . . .164 11-9 output compare registers (ocrh and ocrl). . . . . . . . .165 11-10 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . .166 11-11 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . .168 13-1 overall internal operating frequency range versus resistance for v dd = 5 v 10%, ?0 c to 85 c . . . . . . . . . . . . . .196 13-2 typical internal operating frequency range versus resistance for high v dd operating range, 25 c. . . . . . . . . . . . . .196 13-3 overall internal operating frequency range versus resistance for v dd = 3 v 10%, ?0 c to 85 c . . . . . . . . . . . . . .197 13-4 typical internal operating frequency range versus resistance for low v dd operating range, 25 c. . . . . . . . . . . . . .197 13-5 siop timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 13-6 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . .204 13-7 internal reset timing diagram. . . . . . . . . . . . . . . . . . . . . .205 13-8 low-voltage reset timing diagram. . . . . . . . . . . . . . . . . .205
non-disclosure agreement required list of figures general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 16 list of figures freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor list of tables 17 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 list of tables table title page 4-1 reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . .47 4-2 oscillator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 6-1 oscillator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 7-1 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7-2 port b pin functions ?pb0:pb4 . . . . . . . . . . . . . . . . . . . . . . .91 7-3 port b pin functions ?pb5:pb7 . . . . . . . . . . . . . . . . . . . . . . .98 7-4 port c pin functions (mc68hc05jp6) . . . . . . . . . . . . . . . . .102 8-1 comparator 2 input sources. . . . . . . . . . . . . . . . . . . . . . . . . .107 8-2 channel select bus combinations . . . . . . . . . . . . . . . . . . . . .110 8-3 a/d conversion options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8-4 a/d conversion parameters . . . . . . . . . . . . . . . . . . . . . . . . . .122 8-5 sample conversion timing (v dd = 5.0 vdc) . . . . . . . . . . . . .123 8-6 absolute voltage reading errors . . . . . . . . . . . . . . . . . . . . . .130 8-7 ratiometric voltage reading errors . . . . . . . . . . . . . . . . . . . .132 8-8 voltage comparator setup conditions . . . . . . . . . . . . . . . . . .133 9-1 siop clock rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . .143 10-1 core timer interrupt rates and cop timeout selection . . . .151 10-2 cop watchdog recommendations . . . . . . . . . . . . . . . . . . . .153 11-1 output compare initialization example . . . . . . . . . . . . . . . . .166 12-1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . .176 12-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .177 12-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . .179 12-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . .180
non-disclosure agreement required list of tables general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 18 list of tables freescale semiconductor table title page 12-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 19 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6 v dd and v ss pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7 osc1 and osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.7.2 ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . . .27 1.7.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.7.5 internal low-power oscillator . . . . . . . . . . . . . . . . . . . . . . .28 1.8 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.9 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.10 pa0?a5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.11 pb0?b7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.12 pc0?c7 (mc68hc05jp6) . . . . . . . . . . . . . . . . . . . . . . . . . . .30
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 20 general description freescale semiconductor 1.2 introduction the freescale mc68hc05jj6 and mc68hc05jp6 are rom versions of the m68hc705jj and m68hc705jp families of microcontrollers. 1.3 features low-cost, hc05 core mcu in 20-pin package (mc68hc05jj6) or 28-pin package (mc68hc05jp6) 6160 bytes of user rom, including 8 bytes of security code and 16 bytes of user vectors 224 bytes of low-power user ram (4 transistor ram) 16-bit programmable timer with input capture and output compare 15-stage core timer, including 8-bit free-running counter and 4-stage, selectable real-time interrupt generator simple serial input/output port (siop) with interrupt capability two voltage comparators which can be combined with the 16- bit programmable timer to create a 4-channel, single-slope analog-to-digital (a/d) converter voltage comparator 1 output can drive the pb4 port pin directly under software control 14 input/output (i/o) lines (mc68hc05jj6) or 22 i/o lines (mc68hc05jp6), including high-source/sink current capability on six i/o pins (mc68hc05jj6) or 14 i/o pins (mc68hc05jp6) mask option selectable software programmable pulldowns on all i/o pins and keyboard scan interrupt on four i/o pins software mask and request bit for irq interrupt with mask option selectable sensitivity on irq interrupt (edge- and level-sensitive or edge-only)
general description mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 21 non-disclosure agreement required rom security bytes 1 to aid in locking out access to rom array mask option selectable computer operating properly (cop) watchdog system on-chip temperature measurement diode mask option selectable low-voltage inhibit to reset cpu in low- voltage conditions on-chip oscillator with device selection of crystal/ceramic resonator or rc operation and mask option selectable shunt resistor, approximately 2 m ? internal oscillator for lower-power operation, approximately 100 khz (500 khz selected as a mask option) power-saving stop mode and wait mode instructions (mask option selectable stop conversion to halt and separate mask option for fast 16-cycle restart) illegal address reset internal steering diode and pullup device on reset pin to v dd 1.4 mask options these mc68hc05jj6/mc68hc05jp6 mask options are available: sensitivity on external interrupt, edge-triggered or edge- and level-triggered analog options: comparator 1 output, internal only or internal and pb4 pin sample and hold offset, none of nominal 100 mv oscillator startup delay, 16 or 4064 cycles of internal bus cycles stop instruction: enabled or disabled (converted to halt instruction) 1. no security feature is absolutely secure. however, freescale? strategy is to make reading or copying the rom difficult for unauthorized users.
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 22 general description freescale semiconductor on-chip oscillator type, crystal/ceramic resonator connections or resistor-capacitor (rc) connections oscillator shunt resistor, none or nominal 2 m ? low-voltage reset, enabled or disabled cop watchdog timer, enabled or disabled port a external interrupt capability: enabled or disabled nominal frequency of internal low-power oscillator, 100 or 500 khz software pulldown inhibit, enabled or disabled note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. the exact values and their tolerance or limits are specified in section 13. electrical specifications . 1.5 functional pin description refer to figure 1-2 for the pinouts of the mc68hc05jj6 and mc68hc05jp6 in the user mode . a description of the general function of each pin is discussed here.
general description mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 23 non-disclosure agreement required figure 1-1. user mode block diagram 2 simple serial interface (siop) transfer control stk ptr watchdog & illegal addr detect 16-bit timer (1) input capture (1) output compare external oscillator cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 reset osc1 osc2 static ram (4t) ?224 bytes irq alu 68hc05 cpu accum program counter cpu registers pa0*? pa1*? pa2*? pa3*? pa4* port a data dir reg port a pb4/an4/tcmp/cmp1* pb3/an3/tcap user rom ?6160 bytes pb2/an2 pb1/an1 pb0/an0 15-stage core timer system internal oscillator int int v ss v dd + comparator control & multiplexer tcmp v dd current source + comp2 comp1 tcap int pb7/sck pb6/sdi pb5/sdo pa5* lvr port b port b data dir reg ocf tof icf temperature diode v ss pc3** pc4** pc5** pc6** pc7** pc0** pc1** pc2** port c port c data dir reg port c only on 28-pin mc68hc05jp6 v ss * 15 ma sink capability, maximum of 40 ma into entire port 5 ma source capability, maximum of 20 ma for entire port ** 15 ma sink capability, maximum of 60 ma into entire port 5 ma source capability, maximum of 30 ma for entire port ?irq interrupt capability
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 24 general description freescale semiconductor figure 1-2. user mode pinouts * denotes 10 ma sink /5 ma source capability ? denotes irq interrupt capability pb0/an0 28 v dd 27 26 25 osc2 24 pc3* 23 pc2* 22 pc1* 21 pb1/an1 1 pb2/an2 2 pb3/an3/tcap 3 *pb4/an4/tcmp/cmp1 4 pb5/sdo 5 * pc4 6 *pc5 7 * pc6 8 pc0* 20 reset 19 *pc7 9 pb6/sdi 10 v ss osc1 irq 18 pa0* ? 17 pb7/sck 11 *pa5 12 pa1* ? 16 pa2* ? 15 * pa4 13 ? * pa3 14 pb0/an0 20 v dd 19 18 17 osc2 16 pb1/an1 1 pb2/an2 2 pb3/an3/tcap 3 *pb4/an4/tcmp/cmp1 4 pb5/sdo 5 reset 15 pb6/sdi 6 v ss osc1 irq 14 pa0* ? 13 pb7/sck 7 *pa5 8 pa1* ? 12 pa2* ? 11 * pa4 9 ? * pa3 10 mc68hc05jj6 mc68hc05jp6
general description mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 25 non-disclosure agreement required 1.6 v dd and v ss pins power is supplied to the mcu through v dd and v ss .v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency characteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.7 osc1 and osc2 pins the osc1 and osc2 pins are the connections for the external pin oscillator (epo). the osc1 and osc2 pins can accept these sets of components: 1. a crystal as shown in figure 1-3 (a) 2. a ceramic resonator as shown in figure 1-3 (a) 3. an external resistor as shown in figure 1-3 ( b) 4. an external clock signal as shown in figure 1-3 (c) the selection of the crystal/ceramic resonator or rc oscillator configuration is done by product part number selection as described in section 15. ordering information . the frequency, f osc , of the epo or external clock source is divided by two to produce the internal operating frequency, f op . an internal 2 m ? resistor may be selected between osc1 and osc2 by the shunt resistor mask option.
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 26 general description freescale semiconductor figure 1-3. epo oscillator connections 1.7.1 crystal oscillator the circuit in figure 1-3 (a) shows a typical oscillator circuit for an at- cut, parallel resonant crystal. the crystal manufacturer? recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. an internal startup resistor of approximately 2 m ? can be provided by the shunt resistor mask option between osc1 and osc2 for the crystal type oscillator. the crystal configuration is enabled by choosing the crystal selection in the oscillator connections mask option. note: in general, a 32-khz crystal is not recommended for use with the epo on the mc68hc05jj6/mc68hc05jp6 unless specifically indicated by the crystal manufacturer. mcu (a) crystal or ceramic resonator connections osc1 osc2 2 m ? r unconnected external clock (b) rc oscillator connections (c) external clock source connection osc1 osc2 mcu osc1 osc2 mcu
general description mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 27 non-disclosure agreement required 1.7.2 ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-3 (a) can be used for a ceramic resonator. the resonator manufacturer? recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. an internal startup resistor of approximately 2 m ? can be provided by the shunt resistor mask option between osc1 and osc2 for the ceramic resonator type oscillator. the ceramic resonator configuration is enabled by choosing the crystal selection in the connections oscillator mask option. 1.7.3 rc oscillator the lowest cost oscillator is the rc oscillator configuration where a resistor is connected between the two oscillator pins as shown in figure 1-3 (b) . the internal startup resistor of approximately 2 m ? is not recommended between osc1 and osc2 for the rc-type oscillator. the rc oscillator configuration is selected by the oscillator connections mask option. 1.7.4 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-3 (c) . this configuration is possible regardless of whether the crystal/ceramic resonator or rc oscillator configuration is used.
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 28 general description freescale semiconductor 1.7.5 internal low-power oscillator an internal low-power oscillator (lpo) is provided which has a nominal frequency of 100 khz. this oscillator can be selected via software in place of the external oscillator which uses external components connected to the osc1 and osc2 pins. when operating from this internal lpo, the other oscillator can be powered down by software to further conserve power. all standard parts, whether 20 pin, 28 pin, rc option, or crystal, have the nominal frequency of 100 khz for the lpo. however, a 500-khz frequency lpo is available also. either the 100-khz or the 500-khz lpo is selected by the low-power oscillator mask option. 1.8 reset pin the reset pin can be used as an input to reset the mcu to a known startup state by pulling it to the low state. it also functions as an output to indicate that an internal cop watchdog, illegal address, or low-voltage reset has occurred. the reset pin contains a pullup device to allow the pin to be left disconnected without an external pullup resistor. the reset pin also contains a steering diode that, when the power is removed, will discharge to v dd any charge left on an external capacitor connected between the reset pin and v ss . the reset pin also contains an internal schmitt trigger to improve its noise immunity as an input. 1.9 irq pin the irq input pin drives the asynchronous irq interrupt function of the cpu. using a mask option, the irq interrupt function uses either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if level-sensitive triggering is selected, the irq pin requires an external resistor to v dd for ?ired-or operation. if the irq pin is not used, it must be tied to the v dd supply. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. the voltage on this pin may affect the mode of operation if the
general description mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor general description 29 non-disclosure agreement required voltage on the irq pin is above v dd when the device is released from a reset condition. note: each of the pa0 through pa3 i/o pins may be connected by the port a interrupt mask option as an or function with the irq interrupt function. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin, except that active transitions and levels are inverted. the edge or level sensitivity selected by the mask option for the irq pin also applies to the i/o pins that are ored to create the irq signal. for more information, refer to 4.6 external interrupts . 1.10 pa0?a5 these six i/o lines comprise port a, a general-purpose bidirectional i/o port. this port also has four pins which have keyboard interrupt capability. all six of these pins have high current source and sink capability. all of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option. 1.11 pb0?b7 these eight i/o lines comprise port b, a general-purpose bidirectional i/o port. this port is also shared with the 16-bit programmable timer input capture and output compare functions, with the two voltage comparators in the analog subsystem and with the simple serial interface (siop). the outputs of voltage comparator 1 can directly drive the pb4 pin when enabled by mask option; and the pb4 pin has high current source and sink capability. all of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option.
non-disclosure agreement required general description general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 30 general description freescale semiconductor 1.12 pc0?c7 (mc68hc05jp6) these eight i/o lines comprise port c, a general-purpose bidirectional i/o port. this port is only available on the 28-pin mc68hc05jp6. all eight of these pins have high current source and sink capability. all of these pins have software programmable pulldowns which can be disabled by the software pulldown inhibit mask option.
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor memory 31 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.4 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.5 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.6 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.7 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8 rom security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.9 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.2 introduction this section describes the organization of the memory on the mc68hc05jj6/mc68hc05jp6. 2.3 memory map the cpu can address eight kbytes of memory space as shown in figure 2-1 . the rom portion of memory holds the program instructions, fixed data, user-defined vectors, and interrupt service routines. the ram portion of memory holds variable data. i/o registers are memory mapped so that the cpu can access their locations in the same way that it accesses all other memory locations.
non-disclosure agreement required memory general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 32 memory freescale semiconductor 2.4 input/output registers the first 32 addresses of the memory space, $0000?001f, contain the i/o registers section as summarized in figure 2-2 . one i/o register is located outside the 32-byte i/o section, which is the computer operating properly (cop) register mapped at $1ff0. the assignment of each control, status, and data bit in the i/o register space from $0000?001f is given in figure 2-3 and figure 2-4 . $0000 i/o registers 32 bytes $001f $0020 user ram 224 bytes stack ram 64 bytes $00c0 $00ff $00ff $0100 unimplemented 1536 bytes $06ff $0700 user rom 6136 bytes $1ef7 $1ef8 security check rom 8 bytes $1eff $1f00 internal test rom 240 bytes $1fef $1ff0 user vectors (rom) 16 bytes $1fff figure 2-1. memory map
memory mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor memory 33 non-disclosure agreement required * features related to port c are available only on the 28-pin mc68hc05jp6 devices. address register name $0000 port a data register $0001 port b data register $0002 port c data register * $0003 analog mux register $0004 port a data direction register $0005 port b data direction register $0006 port c data direction register * $0007 unused $0008 core timer status & control register $0009 core timer counter $000a serial control register $000b serial status register $000c serial data register $000d irq status & control register $000e unused $000f unused $0010 port a and port c pulldown register * $0011 port b pulldown register $0012 timer control register $0013 timer status register $0014 input capture register (msb) $0015 input capture register (lsb) $0016 output compare register (msb) $0017 output compare register (lsb) $0018 timer counter register (msb) $0019 timer counter register (lsb) $001a alternate counter register (msb) $001b alternate counter register (lsb) $001c unused $001d analog control register $001e analog status register $001f reserved figure 2-2. i/o registers
non-disclosure agreement required memory general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 34 memory freescale semiconductor * features related to port c are available only on the 28-pin mc68hc05jp6 devices. addr. register bit 7 6 5 4321 bit 0 $0000 port a data, porta read: 0 0 pa5 pa4 pa3 pa2 pa1 pa0 write: $0001 port b data, portb read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: $0002 * port c data, portc read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: $0003 analog mux register, amux read: hold dhold inv vref mux4 mux3 mux2 mux1 write: $0004 port a data direction, ddra read: 0 0 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0005 port b data direction, ddrb read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: $0006 * port c data direction, ddrc read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: $0007 unimplemented read: write: $0008 core timer status/control, ctscr read: ctof rtif ctofe rtie 00 rt1 rt0 write: ctofr rtifr $0009 core timer counter, ctcr read: bit 7 6 5 4321 bit 0 write: $000a serial control, scr read: spie spe lsbf mstr 0 cpha spr1 spr0 write: spir $000b serial status, ssr read: spif dcol 0 00000 write: $000c serial data, sdr read: bit 7 6 5 4321 bit 0 write: $000d irq status & control, iscr read: irqe om2 om1 0 irqf 0 0 0 write: r irqr $000e unimplemented read: write: $000f unimplemented read: write: = unimplemented r = reserved figure 2-3. i/o registers $0000?000f
memory mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor memory 35 non-disclosure agreement required * features related to port c are available only on the 28-pin mc68hc05jp6 devices. addr. register r/w bit 7 6 5 4 3 2 1 bit 0 $0010 * port a & port c pulldown, pdra read: write: pdich pdicl pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 $0011 port b pulldown, pdrb read: write: pdib7 pdib6 pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 $0012 timer control, tcr read: icie ocie toie 000 iedg olvl write: $0013 timer status, tsr read: icf ocf tof 00000 write: $0014 input capture msb, icrh read: bit15 14 13 12 11 10 9 bit8 write: $0015 input capture lsb, icrl read: bit7 6 5 4 3 2 1 bit0 write: $0016 output compare msb, ocrh read: bit15 14 13 12 11 10 9 bit 8 write: $0017 output compare lsb, ocrl read: bit 7 6 5 4 3 2 1 bit 0 write: $0018 timer counter msb, tmrh read: bit15 14 13 12 11 10 9 bit 8 write: $0019 timer counter lsb, tmrl read: bit 7 6 5 4 3 2 1 bit 0 write: $001a alternate counter msb, acrh read: bit15 14 13 12 11 10 9 bit 8 write: $001b alternate counter lsb, acrl read: bit 7 6 5 4 3 2 1 bit 0 write: $001c unimplemented read: write: $001d analog control, acr read: chg atd2 atd1 icen cpie cp2en cp1en isen write: $001e analog status, asr read: cpf2 cpf1 0 0 coe1 voff cmp2 cmp1 write: cpfr2 cpfr1 r $001f reserved read: r r r r rrrr write: r r r r rrrr = unimplemented r = reserved figure 2-4. i/o registers $0010?001f
non-disclosure agreement required memory general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 36 memory freescale semiconductor 2.5 interrupt vector mapping the interrupt vectors are contained in the upper memory addresses above $1ff0 as shown in figure 2-5 . 2.6 ram the 224 addresses from $0020 to $00ff serve as both the user ram and the stack ram. the cpu uses five ram bytes to save all cpu register contents before processing an interrupt. during a subroutine call, the cpu uses two bytes to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. address register name $1ff0 cop register $1ff1 unused $1ff2 analog interrupt vector (msb) $1ff3 analog interrupt vector (lsb) $1ff4 serial interrupt vector (msb) $1ff5 serial interrupt vector ((lsb) $1ff6 timer interrupt vector (msb) $1ff7 timer interrupt vector (lsb) $1ff8 ctimer interrupt vector (msb) $1ff9 ctimer interrupt vector (lsb) $1ffa external irq vector (msb) $1ffb external irq vector (lsb) $1ffc swi vector (msb) $1ffd swi vector (lsb) $1ffe reset vector (msb) $1fff reset vector (lsb) figure 2-5. vector mapping
memory mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor memory 37 non-disclosure agreement required 2.7 rom the rom is located in three areas of the memory map: addresses $0700?1ef7 contain 6136 bytes of user rom. addresses $1ef8?1eff contain eight bytes for security code. addresses $1ff0?fff contain 16 bytes of rom reserved for user vectors and cop register. 2.8 rom security the mc68hc05jj6/mc68hc05jp6 contains a rom security feature 1 that requires that the proper data sequence be presented to port b before the internal rom contents can be read in any of the expanded bus modes used for testing. the bytes to match are placed at rom locations $1ef8 through $1eff as shown in figure 2-6 . 1. no security feature is absolutely secure. however, freescale? strategy is to make reading or copying the rom difficult for unauthorized users. address register name $1ef8 1st rom security check byte $1ef9 2nd rom security check byte $1efa 3rd rom security check byte $1efb 4th rom security check byte $1efc 5th rom security check byte $1efd 6th rom security check byte $1efe 7th rom security check byte $1eff 8th rom security check byte figure 2-6. rom security bytes
non-disclosure agreement required memory general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 38 memory freescale semiconductor 2.9 cop register as shown in figure 2-7 , a register location is provided at $1ff0 to reset the cop watchdog timer. $1ff0 bit 7 6 54321 bit 0 read: write: copc reset: unaffected by reset = unimplemented figure 2-7. cop register (copr)
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor central processor unit (cpu) 39 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.5 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.6 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.7 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.8 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
non-disclosure agreement required central processor unit (cpu) general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 40 central processor unit (cpu) freescale semiconductor 3.2 introduction this section describes the cpu registers. figure 3-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 3-1. 68hc05 programming model 3.3 accumulator the accumulator is a general-purpose 8-bit register as shown in figure 3-2 . the cpu uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. accumulator (a) a index register (x) x sp 11 00 00 0 00 0 pcl pch 11 1 zc in 1h 11 0 4 75 condition code register (ccr) program counter (pc) stack pointer (sp) 0 7 8 15 15 5 7 7 0 0 0 half-carry flag interrupt mask negative flag zero flag carry/borrow flag 10 6 bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 3-2. accumulator (a)
central processor unit (cpu) mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor central processor unit (cpu) 41 non-disclosure agreement required 3.4 index register the index register is a general-purpose 8-bit register as shown in figure 3-3 . in the indexed addressing modes, the cpu uses the byte in the index register to determine the conditional address of the operand. the 8-bit index register can also serve as a temporary data storage location. 3.5 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack as shown in figure 3-4 . during a reset or after the reset stack pointer (rsp) instruction, the stack pointer initializes to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. the 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations; an interrupt uses five locations. bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 3-3. index register (x) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: 0000000011 write: reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 figure 3-4. stack pointer (sp)
non-disclosure agreement required central processor unit (cpu) general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 42 central processor unit (cpu) freescale semiconductor 3.6 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched as shown in figure 3-5 . the three most significant bits of the program counter are ignored internally and appear as 111 during stacking and subroutine calls. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.7 condition code register the condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111 as shown in figure 3-6 . the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. the following paragraphs describe the functions of the condition code register. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: 111 write: reset: 0 0 0 loaded with vector from $1ffe and $1fff figure 3-5. program counter (pc) bit 7 654321 bit 0 read: 111hincz write: reset: 1 1 1 u 1 u u u u = unaffected figure 3-6. condition code register (ccr)
central processor unit (cpu) mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor central processor unit (cpu) 43 non-disclosure agreement required half-carry flag (h) the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary coded decimal (bcd) arithmetic operations. reset has no effect on the half-carry flag. interrupt mask (i) setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is a logic zero, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after a reset, the interrupt mask is set and can be cleared only by a cli instruction. negative flag (n) the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. reset has no effect on the negative flag. zero flag (z) the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. reset has no effect on the zero flag. carry/borrow flag (c) the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag. reset has no effect on the carry/borrow flag.
non-disclosure agreement required central processor unit (cpu) general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 44 central processor unit (cpu) freescale semiconductor 3.8 arithmetic/logic unit (alu) the alu performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction (mul) requires 11 internal clock cycles to complete this chain of operations.
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 45 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.5 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.1 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6.2 pa0?a3 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.6.3 irq status and control register. . . . . . . . . . . . . . . . . . . . .53 4.7 core timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.7.1 core timer overflow interrupt. . . . . . . . . . . . . . . . . . . . . . .55 4.7.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.8 programmable timer interrupts . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.1 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.2 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.9 serial interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.10 analog interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.10.1 comparator input match interrupt . . . . . . . . . . . . . . . . . . . .58 4.10.2 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 46 interrupts freescale semiconductor 4.2 introduction an interrupt temporarily stops normal program execution to process a particular event. an interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. interrupt processing automatically saves the cpu registers on the stack and loads the program counter with a user-defined vector address. 4.3 interrupt vectors table 4-1 summarizes the reset and interrupt sources and vector assignments.
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 47 non-disclosure agreement required note: if more than one interrupt request is pending, the cpu fetches the vector of the higher priority interrupt first. a higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the i bit. table 4-1. reset/interrupt vector addresses function source mask options global hardware mask local software mask priority (1 = highest) vector address reset power-on logic reset pin low-voltage reset illegal address reset 1 $1ffe?1fff cop watchdog enable software interrupt (swi) user code same priority as instruction $1ffc?1ffd external interrupt (irq) irq pin i bit irqe bit 2 $1ffa?1ffb pa3 pin pa2 pin pa1 pin pa0 pin enable core timer interrupts tof bit rtif bit i bit tofe bit rtie bit 3 $1ff8?1ff9 programmable timer interrupts icf bit ocf bit tof bit i bit icie bit ocie bit toie bit 4 $1ff6?1ff7 serial interrupt spif bit i bit spie bit 5 $1ff4?1ff5 analog interrupt cpf1 bit cpf2 bit i bit cpie bit 6 $1ff2?1ff3
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 48 interrupts freescale semiconductor 4.4 interrupt processing the cpu does these actions to begin servicing an interrupt: stores the cpu registers on the stack in the order shown in figure 4-1 sets the i bit in the condition code register to prevent further interrupts loads the program counter with the contents of the appropriate interrupt vector locations as shown in table 4-1 the return-from-interrupt (rti) instruction causes the cpu to recover its register contents from the stack as shown in figure 4-1 . the sequence of events caused by an interrupt is shown in the flowchart in figure 4-2 . $0020 bottom of ram $0021 $00be $00bf $00c0 bottom of stack $00c1 $00c2 unstacking order ? n condition code register 5 1 n+1 accumulator 4 2 n+2 index register 3 3 n+3 program counter (high byte) 2 4 n+4 program counter (low byte) 1 5 ? stacking $00fd order $00fe $00ff top of stack (ram) figure 4-1. interrupt stacking order
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 49 non-disclosure agreement required figure 4-2. interrupt flowchart no external interrupt? i bit set? from reset yes yes clear irq latch no execute instruction unstack ccr, a, x, pch, pcl fetch next instruction stack pcl, pch, x, a, ccr set i bit load pc with interrupt vector core timer interrupt? yes no timer interrupt? yes no serial interrupt? yes no analog interrupt? yes no swi instruction? yes no rti instruction? yes no
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 50 interrupts freescale semiconductor 4.5 software interrupt the software interrupt (swi) instruction causes a non-maskable interrupt. 4.6 external interrupts these sources can generate external interrupts: irq pin pa3?a0 pins setting the i bit in the condition code register or clearing the irqe bit in the interrupt status and control register disables these external interrupts. 4.6.1 irq pin an interrupt signal on the irq pin latches an external interrupt request. to help clean up slow edges, the input from the irq pin is processed by a schmitt trigger gate. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register (ccr) and the irqe bit in the irq status and control register (iscr). if the i bit is clear and the irqe bit is set, then the cpu begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 4-3 shows the logic for external interrupts. note: if the irq pin is not in use, it should be connected to the v dd pin. the irq pin can be negative edge-triggered only or negative edge- and low level-triggered. this external interrupt sensitivity is selected with the external interrupt sensitivity mask option.
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 51 non-disclosure agreement required with the edge- and level-sensitive trigger option, a falling edge or a low level on the irq pin latches an external interrupt request. the edge- and level-sensitive trigger mask option allows connection to the irq pin of multiple wired-or interrupt sources. as long as any source is holding the irq low, an external interrupt request is present, and the cpu continues to execute the interrupt service routine. with the edge-sensitive-only trigger mask option, a falling edge on the irq pin latches an external interrupt request. a subsequent interrupt request can be latched only after the voltage level on the irq pin returns to a logic one and then falls again to logic zero. figure 4-3. external interrupt logic pa3 pa2 pa1 pa0 irq latch v dd rst irq vector fetch irq status/control register ($000d) external interrupt request irqe irqf irqr internal data bus to bih & bil instruction processing r irq keyboard interrupt mask option edge- or edge- and level mask option (enable = 1) (enable=1)
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 52 interrupts freescale semiconductor note: the response of the irq pin can be affected if the external interrupt capability of the pa0 through pa3 pins is enabled by mask option. if the port a pins are enabled as external interrupts, then any high level on a pa0 through pa3 pin will cause the irq changes and state to be ignored until all of the pa0 through pa3 pins have returned to a low level. 4.6.2 pa0?a3 pins the port a interrupt mask option that enables the pa0 through pa3 pins (pa0:pa3) to serve as additional external interrupt sources is available. when this mask option is enabled, a rising edge on a pa0:pa3 pin latches an external interrupt request. after completing the current instruction, the cpu tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the iscr. if the i bit is clear and the irqe bit is set, the cpu then begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. the pa0:pa3 pins can be edge-triggered or edge- and level-triggered depending upon the mask option selection for the irq pin. with the edge- and level-sensitive trigger mask option, a rising edge or a high level on a pa0:pa3 pin latches an external interrupt request. the edge- and level-sensitive trigger mask option allows connection to a pa0:pa3 pin of multiple wired-or interrupt sources. as long as any source is holding the pin high, an external interrupt request is present, and the cpu continues to execute the interrupt service routine. with the edge-sensitive only trigger mask option, a rising edge on a pa0:pa3 pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to a logic zero and then rises again to a logic one.
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 53 non-disclosure agreement required note: if the port a pins are enabled by mask option as external interrupts, then a high level on any pa0:pa3 pin will drive the state of the irq function such that the irq pin and other pa0:pa3 pins will be ignored until all of the pa0:pa3 pins have returned to a low level. similarly, if the irq pin is at a low level, the pa0:pa3 pins will be ignored until the irq pin returns to a high state. 4.6.3 irq status and control register the irq status and control register (iscr), shown in figure 4-4 , contains an external interrupt mask (irqe), an external interrupt flag (irqf), and a flag reset bit (irqr). unused bits will read as logic zeros. the iscr also contains two control bits for the oscillators, external pin oscillator, and internal low-power oscillator. reset sets the irqe and om2 bits; and clears all the other bits. irqe ?external interrupt request enable this read/write bit enables external interrupts. reset sets the irqe bit. 1 = external interrupt processing enabled 0 = external interrupt processing disabled om1 and om2 ?oscillator selects these bits control the selection and enabling of the oscillator source for the mcu. one choice is the internal low-power oscillator (lpo). the other choice is the external pin oscillator (epo) which is common to most mc68hc05 mcu devices. the epo uses external $000d bit 7 654321 bit 0 read: irqe om2 om1 0 irqf 0 0 0 write: r irqr reset: 110000u0 = unimplemented r = reserved figure 4-4. irq status and control register (iscr)
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 54 interrupts freescale semiconductor components like filter capacitors and a crystal or ceramic resonator and consumes more power. the selection and enable conditions for these two oscillators are shown in table 4-2 . therefore, the lowest power is consumed when om1 is cleared. the state with both om1 and om2 set is provided so that the epo can be started and allowed to stabilize while the lpo still clocks the mcu. the reset state is for om1 to be cleared and om2 to be set, which selects the lpo and disables the epo. irqf ?external interrupt request flag the irq flag is a clearable, read-only bit that is set when an external interrupt request is pending. writing to the irqf bit has no effect. reset clears the irqf bit. 1 = interrupt request pending 0 = no interrupt request pending these conditions set the irq flag: an external interrupt signal on the irq pin an external interrupt signal on pins pa0, pa1, pa2, or pa3 when the pa0 through pa3 pins are enabled by a mask option to serve as external interrupt sources these conditions clear the irq flag: when the cpu fetches the interrupt vector when a logic one is written to the irqr bit table 4-2. oscillator selection om2 om1 oscillator selected by cpu internal low-power oscillator (lpo) external pin oscillator (epo) power consumption 0 0 internal enabled disabled lowest 0 1 external disabled enabled normal 1 0 internal enabled disabled lowest 1 1 internal enabled enabled normal
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 55 non-disclosure agreement required irqr ?interrupt request reset this write-only bit clears the irqf flag bit and prevents redundant execution of interrupt routines. writing a logic one to irqr clears the irqf. writing a logic zero to irqr has no effect. irqr always reads as a logic zero. reset has no effect on irqr. 1 = clear irqf ?g bit 0 = no effect 4.7 core timer interrupts the core timer can generate the two interrupts: timer overflow interrupt real-time interrupt setting the i bit in the condition code register disables core timer interrupts. the controls and flags for these interrupts are in the core timer status and control register (ctscr) located at $0008. 4.7.1 core timer overflow interrupt an overflow interrupt request occurs if the core timer overflow flag (tof) becomes set while the core timer overflow interrupt enable bit (tofe) is also set. the tof flag bit can be reset by writing a logical one to the ctofr bit in the ctscr or by a reset of the device. 4.7.2 real-time interrupt a real-time interrupt request occurs if the real-time interrupt flag (rtif) becomes set while the real-time interrupt enable bit (rtie) is also set. the rtif flag bit can be reset by writing a logical one to the rtifr bit in the ctscr or by a reset of the device.
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 56 interrupts freescale semiconductor 4.8 programmable timer interrupts the 16-bit programmable timer can generate an interrupt whenever these events occur: input capture output compare timer counter overflow setting the i bit in the condition code register disables timer interrupts. the controls for these interrupts are in the timer control register (tcr) located at $0012 and in the status bits in the timer status register (tsr) located at $0013. 4.8.1 input capture interrupt an input capture interrupt occurs if the input capture flag (icf) becomes set while the input capture interrupt enable bit (icie) is also set. the icf flag bit is in the tsr, and the icie enable bit is located in the tcr. the icf flag bit is cleared by a read of the tsr with the icf flag bit set and then followed by a read of the lsb of the input capture register (icrl) or by reset. the icie enable bit is unaffected by reset. 4.8.2 output compare interrupt an output compare interrupt occurs if the output compare flag (ocf) becomes set while the output compare interrupt enable bit (ocie) is also set. the ocf flag bit is in the tsr and the ocie enable bit is in the tcr. the ocf flag bit is cleared by a read of the tsr with the ocf flag bit set, and then followed by an access to the lsb of the output compare register (ocrl) or by reset. the ocie enable bit is unaffected by reset.
interrupts mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor interrupts 57 non-disclosure agreement required 4.8.3 timer overflow interrupt a timer overflow interrupt occurs if the timer overflow flag (tof) becomes set while the timer overflow interrupt enable bit (toie) is also set. the tof flag bit is in the tsr and the toie enable bit is in the tcr. the tof flag bit is cleared by a read of the tsr with the tof flag bit set and then followed by an access to the lsb of the timer registers (tmrl) or by reset. the toie enable bit is unaffected by reset. 4.9 serial interrupts the simple serial interface can generate the two interrupts: receive sequence complete transmit sequence complete setting the i bit in the condition code register disables serial interrupts. the controls for these interrupts are in the serial control register (scr) located at $000a and in the status bits in the serial status register (ssr) located at $000b. a transfer complete interrupt occurs if the serial interrupt flag (spif) becomes set while the serial interrupt enable bit (spie) is also set. the spif flag bit is in the serial status register (ssr) located at $000b, and the spie enable bit is located in the serial control register (scr) located at $000a. the spif flag bit is cleared by a read of the ssr with the spif flag bit set, and then followed by a read or write to the serial data register (sdr) located at $000c. the spif flag bit can also be reset by writing a one to the spir bit in the scr.
non-disclosure agreement required interrupts general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 58 interrupts freescale semiconductor 4.10 analog interrupts the analog subsystem can generate these interrupts: voltage on positive input of comparator 1 is greater than the voltage on the negative input of comparator 1. voltage on positive input of comparator 2 is greater than the voltage on the negative input of comparator 2. trigger of the input capture interrupt from the programmable timer as described in 4.8.1 input capture interrupt setting the i bit in the condition code register disables analog subsystem interrupts. the controls for these interrupts are in the analog subsystem control register (acr) located at $001d, and the status bits are in the analog subsystem status register (asr) located at $001e. 4.10.1 comparator input match interrupt a comparator input match interrupt occurs if either compare flag bit (cpf1 or cpf2) in the asr becomes set while the comparator interrupt enable bit (cpie) in the acr is also set. the cpf1 and cpf2 flag bits can be reset by writing a one to the corresponding cpfr1 or cpfr2 bits in the asr. reset clears these bits. 4.10.2 input capture interrupt the analog subsystem can also generate an input capture interrupt through the 16-bit programmable timer. the input capture can be triggered when there is a match in the input conditions for the voltage comparator 2. if comparator 2 sets the cp2f flag bit in the asr and the input capture enable (icen) in the acr is set, then an input capture will be performed by the programmable timer. if the icie enable bit in the tcr is also set, then an input compare interrupt will occur. reset clears these bits. note: for the analog subsystem to generate an interrupt using the input capture function of the programmable timer, the icen enable bit in the acr and the icie and iedg bits in the tcr must all be set.
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor resets 59 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.4 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.2 computer operating properly (cop) reset . . . . . . . . . . . .62 5.5.3 low-voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.5.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6 reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.1 cpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.3 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.4 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.6.5 16-bit programmable timer . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.6 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.6.7 analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 external oscillator and internal low-power oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .67
non-disclosure agreement required resets general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 60 resets freescale semiconductor 5.2 introduction this section describes the five reset sources and how they initialize the mcu. a reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. these conditions produce a reset: initial power-up of device (power-on reset) a logic zero applied to the reset pin (external reset) timeout of the cop watchdog (cop reset) low voltage applied to the device (lvr reset) fetch of an opcode from an address not in the memory map (illegal address reset) figure 5-1 shows a block diagram of the reset sources and their interaction. figure 5-1. reset sources reset reset latch r cop watchdog power-on reset illegal address reset internal d internal clock s rst to cpu and low-voltage reset v dd 3-cycle clocked 1-shot subsystems address bus lvr mask option cop mask option (enable = 1) (enable = 1)
resets mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor resets 61 non-disclosure agreement required 5.3 power-on reset a positive transition on the v dd pin generates a power-on reset. the power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. a delay of 16 or 4064 internal bus cycles (t cyc ) after the oscillator becomes active allows the clock generator to stabilize. if the reset pin is at logic zero at the end of this multiple t cyc time, the mcu remains in the reset condition until the signal on the reset pin goes to a logic one. 5.4 external reset a logic zero applied to the reset pin for one and one half t cyc generates an external reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. the external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the internal rst signal that resets the cpu and peripherals. the reset pin can also be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. this reset pulldown device will be asserted only for three to four cycles of the internal bus or as long as the internal reset source is asserted. note: do not connect the reset pin directly to v dd , as this may overload some power supply designs if the internal pulldown on the reset pin should activate.
non-disclosure agreement required resets general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 62 resets freescale semiconductor 5.5 internal resets the four internally generated resets are: initial power-on reset function cop watchdog timer reset low-voltage reset illegal address detector only the cop watchdog timer reset, low-voltage reset, and illegal address detector will also assert the pulldown device on the reset pin for the duration of the reset function or for three to four internal bus cycles, whichever is longer. 5.5.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). depending on a mask option, there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of the 16 or 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. por will not activate the pulldown device on the reset pin. v dd must drop below v por for the internal por circuit to detect the next rise of v dd . 5.5.2 computer operating properly (cop) reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic zero to the copc bit of the cop register at location $1ff0. the cop register, shown in
resets mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor resets 63 non-disclosure agreement required figure 5-2 , is a write-only register that returns the contents of a rom location when read. copc ?cop clear copc is a write-only bit. periodically writing a logic zero to copc prevents the cop watchdog from resetting the mcu. reset clears the copc bit. 1 = no effect on cop watchdog timer 0 = reset cop watchdog timer the cop watchdog reset will assert the pulldown device to pull the reset pin low for three to four cycles of the internal bus. the cop watchdog reset function can be enabled or disabled by the cop watchdog timer mask option. 5.5.3 low-voltage reset (lvr) the lvr activates the rst reset signal to reset the device when the voltage on the v dd pin falls below the lvr trip voltage. the lvr will assert the pulldown device to pull the reset pin low for three to four cycles of the internal bus. the lvr reset function can be enabled or disabled by the low-voltage reset mask option. note: the lvr is guaranteed for applications where the v dd supply voltage normally operates above 4.5 volts. devices that have the lvr mask option selected cannot be operated at the 3-v operating range. $1ff0 bit 7 654321 bit 0 read: write: copc reset: unaffected by reset = unimplemented figure 5-2. cop register (copr)
non-disclosure agreement required resets general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 64 resets freescale semiconductor 5.5.4 illegal address reset an opcode fetch (execution of an instruction) at an address that is not in the rom (locations $0700?1fff) or the ram (locations $0020?00ff) generates an illegal address reset. the illegal address reset will assert the pulldown device to pull the reset pin low for three to four cycles of the internal bus. 5.6 reset states the following paragraphs describe how the various resets initialize the mcu. 5.6.1 cpu a reset has these effects on the cpu: loads the stack pointer with $ff sets the i bit in the condition code register, inhibiting interrupts loads the program counter with the user-defined reset vector from locations $1ffe and $1fff clears the stop latch, enabling the cpu clock clears the wait latch, bringing the cpu out of the wait mode
resets mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor resets 65 non-disclosure agreement required 5.6.2 i/o registers a reset has these effects on i/o registers: clears bits in data direction registers configuring pins as inputs: ddra5?dra0 in ddra for port a ddrb7?drb0 in ddra for port b ddrc7?drc0 in ddrc for port c * clears bits in pulldown inhibit registers to enable pulldown devices: pdia5?dia0 in pdra for port a pdib7?dib0 in pdrb for port b pdich and pdicl in pdra for port c * has no effect on port a, b, or c* data registers sets the irqe bit in the interrupt status and control register (iscr) 5.6.3 core timer a reset has these effects on the core timer: clears the core timer counter register (ctcr) clears the core timer interrupt flag and enable bits in the core timer status and control register (ctscr) sets the real-time interrupt rate selection bits (rt0 and rt1) such that the device will start with the longest real-time interrupt and longest cop timeout delays 5.6.4 cop watchdog a reset clears the cop watchdog timeout counter. * features related to port c are available only on the 28-pin mc68hc705jp6 devices.
non-disclosure agreement required resets general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 66 resets freescale semiconductor 5.6.5 16-bit programmable timer a reset has these effects on the 16-bit programmable timer: initializes the timer counter registers (tmrh and tmrl) to a value of $fffc initializes the alternate timer counter registers (acrh and acrl) to a value of $fffc clears all the interrupt enables and the output level bit (olvl) in the timer control register (tcr) does not affect the input capture edge bit (iedg) in the tcr does not affect the interrupt flags in the timer status register (tsr) does not affect the input capture registers (icrh and icrl) does not affect the output compare registers (ocrh and ocrl) 5.6.6 serial interface a reset has these effects on the serial interface: clears all bits in the siop control register (scr) clears all bits in the siop status register (ssr) does not affect the contents of the siop data register (sdr) a reset, therefore, disables the siop and leaves the shared port b pins as general i/o. any pending interrupt flag is cleared and the siop interrupt is disabled. also the baud rate defaults to the slowest rate.
resets mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor resets 67 non-disclosure agreement required 5.6.7 analog subsystem a reset has these effects on the analog subsystem: clears all the bits in the multiplex register (amux) bits except the hold switch bit (hold) which is set clears all the bits in the analog control register (acr) clears all the bits in the analog status register (asr) a reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is switched to v ss . both comparators are set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. the current source and discharge device on the pb0/an0 pin is disabled and powered down. any analog subsystem interrupt flags are cleared and the analog interrupt is disabled. direct drive by comparator 1 to the pb4 pin and the voltage offset to the sample capacitor are disabled (if both are enabled by the analog options mask option). 5.6.8 external oscillator and internal low-power oscillator a reset presets the oscillator select bits (om1 and om2) in the interrupt status and control register (iscr) such that the device runs from the internal oscillator (om1 = 0, om2 = 1) which has these effects on the oscillators: the internal low-power oscillator is enabled and selected. the external oscillator is disabled. the cpu bus clock is driven from the internal low-power oscillator.
non-disclosure agreement required resets general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 68 resets freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor operating modes 69 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.3 oscillator source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 6.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.4.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.4.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.4.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.4.4 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.2 introduction this section describes the operation of the device with respect to the oscillator source and the low-power modes: stop mode wait mode halt mode data-retention mode
non-disclosure agreement required operating modes general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 70 operating modes freescale semiconductor 6.3 oscillator source the mcu can be clocked by either an internal low-power oscillator (lpo) without external components or by an external pin oscillator (epo) which uses external components. the enable and selection of the clock source is determined by the state of the oscillator select bits (om1 and om2) in the interrupt status and control register (iscr) as shown in figure 6-1 . irqe ?external interrupt request enable this read/write bit enables external interrupts. refer to section 4. interrupts for more details. om1 and om2 ?oscillator selects these bits control the selection and enabling of the oscillator source for the mcu. one choice is the internal lpo and the other oscillator is the epo which is common to most mc68hc05 mcu devices. the epo uses external components like filter capacitors and a crystal or ceramic resonator and consumes more power than the lpo. the selection and enable conditions for these two oscillators are shown in table 6-1 . reset clears om1 and sets om2, which selects the lpo and disables the epo. . $000d bit 7 654321 bit 0 read: irqe om2 om1 0 irqf 0 0 0 write: r irqr reset: 110000u0 = unimplemented r = reserved u = unaffected figure 6-1. irq status and control register (iscr) table 6-1. oscillator selection om2 om1 oscillator selected internal low-power oscillator (lpo) external pin oscillator (epo) power consumption 0 0 internal enabled disabled lowest 0 1 external disabled enabled normal 1 0 internal enabled disabled lowest 1 1 internal enabled enabled normal
operating modes mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor operating modes 71 non-disclosure agreement required therefore, the lowest power is consumed when om1 is cleared. the state with both om1 and om2 set is provided so that the epo can be started up and allowed to stabilize while the lpo still clocks the mcu. note: when switching between oscillators, the user must be careful to ensure that the newly selected oscillator has been enabled and powered up long enough to stabilize before shifting clock sources. always select the case where both om1 and om2 are set and remain at this state for at least 4096 epo clock cycles if going from the lpo to the epo or 16 lpo cycles if going from the epo to the lpo. irqf ?external interrupt request flag the irqf flag is a clearable, read-only bit that is set when an external interrupt request is pending. refer to section 4. interrupts for more details. irqr ?interrupt request reset this write-only bit clears the irqf flag bit and prevents redundant execution of interrupt routines. refer to section 4. interrupts for more details. 6.4 low-power modes four modes of operation reduce power consumption: stop mode wait mode halt mode data-retention mode figure 6-2 shows the sequence of events in stop, wait, and halt modes.
non-disclosure agreement required operating modes general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 72 operating modes freescale semiconductor figure 6-2. stop/wait/halt flowchart stop halt mask option? clear i bit in ccr set irqe bit in iscr clear ctof, rtif, ctofe, and rtie bits in tscr disable external pin oscillator external reset? external interrupt? no no no turn on selected oscillator reset stabilization delay timer yes yes halt yes end of stabilization delay? yes no no external reset? clear i bit in ccr set irqe bit in iscr turn off cpu clock keep other module yes wait turn on cpu clock 1. load pc with reset vector or 2. service interrupt a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector turn off internal low-power oscillator clear icf, ocf, and tof bits in tsr clear icie, ocie, and toie bits in tcr clocks active no core interrupt? yes timer no external interrupt? yes no prog. interrupt? yes timer no siop interrupt? yes no interrupt? yes analog no cop reset? yes clear i bit in ccr set irqe bit in iscr turn off cpu clock keep other module clocks active no external reset? yes no core interrupt? yes timer no external interrupt? yes no prog. interrupt? yes timer no siop interrupt? yes no yes no cop reset? yes interrupt? analog
operating modes mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor operating modes 73 non-disclosure agreement required 6.4.1 stop mode the stop instruction puts the mcu in a mode with the lowest power consumption and affects the mcu as follows: turns off the cpu clock and all internal clocks by stopping both the external pin oscillator and the internal low-power oscillator. the selection of the oscillator by the om1 and om2 bits in the iscr is not affected. the stopped clocks turn off the cop watchdog, the core timer, the programmable timer, the analog subsystem, and the siop. removes any pending core timer interrupts by clearing the core timer interrupt flags (ctof and rtif) in the core timer status and control register (ctscr) disables any further core timer interrupts by clearing the core timer interrupt enable bits (ctofe and rtie) in the ctscr removes any pending programmable timer interrupts by clearing the timer interrupt flags (icf, ocf, and tof) in the timer status register (tsr) disables any further programmable timer interrupts by clearing the timer interrupt enable bits (icie, ocie, and toie) in the timer control register (tcr) enables external interrupts via the irq pin by setting the irqe bit in the irq status and control register (iscr). external interrupts are also enabled via the pa0 through pa3 pins, if the port a interrupts are enabled by the port a interrupt mask option. enables interrupts in general by clearing the i bit in the condition code register the stop instruction does not affect any other bits, registers, or i/o lines. these conditions bring the mcu out of stop mode: an external interrupt signal on the irq pin ?a high-to-low transition on the irq pin loads the program counter with the contents of locations $1ffa and $1ffb.
non-disclosure agreement required operating modes general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 74 operating modes freescale semiconductor an external interrupt signal on a port a external interrupt pin if selected by a mask option, a low-to-high transition on a pa3?a0 pin loads the program counter with the contents of locations $1ffa and $1ffb. external reset ?a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. when the mcu exits stop mode, processing resumes after a stabilization delay of 16 or 4064 internal bus cycles, depending on the selection of the oscillator startup delay mask option. note: execution of the stop instruction without using the mask option to make it a halt instruction will cause the oscillators to stop, and, therefore, disable the cop watchdog timer. if the cop watchdog timer is to be used, stop mode should be changed to halt mode as described in 6.4.3 halt mode . 6.4.2 wait mode the wait instruction puts the mcu in a low-power wait mode which consumes more power than the stop mode and affects the mcu as follows: enables interrupts by clearing the i bit in the condition code register enables external interrupts by setting the irqe bit in the irq status and control register stops the cpu clock which drives the address and data buses, but allows the selected oscillator to continue to clock the core timer, programmable timer, analog subsystem, and siop the wait instruction does not affect any other bits, registers, or i/o lines.
operating modes mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor operating modes 75 non-disclosure agreement required these conditions restart the cpu bus clock and bring the mcu out of wait mode: an external interrupt signal on the irq pin ?a high-to-low transition on the irq pin loads the program counter with the contents of locations $1ffa and $1ffb. an external interrupt signal on a port a external interrupt pin if selected by a mask option, a low-to-high transition on a pa3?a0 pin loads the program counter with the contents of locations $1ffa and $1ffb. a core timer interrupt ?a core timer overflow or a real-time interrupt loads the program counter with the contents of locations $1ff8 and $1ff9. a programmable timer interrupt a programmable timer interrupt driven by an input capture, output compare, or timer overflow loads the program counter with the contents of locations $1ff6 and $1ff7. an siop interrupt ?an siop interrupt driven by the completion of transmitted or received 8-bit data loads the program counter with the contents of locations $1ff4 and $1ff5. an analog subsystem interrupt an analog subsystem interrupt driven by a voltage comparison loads the program counter with the contents of locations $1ff2 and $1ff3. a cop watchdog reset a timeout of the cop watchdog resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. software can enable real-time interrupts so that the mcu can periodically exit the wait mode to reset the cop watchdog. an external reset ?a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. when the mcu exits wait mode, there is no delay before code executes; however, a delay does occur when exiting stop or halt modes.
non-disclosure agreement required operating modes general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 76 operating modes freescale semiconductor 6.4.3 halt mode the stop instruction puts the mcu in halt mode if selected by the stop mask option. halt mode is identical to wait mode, except that a variable recovery delay occurs when the mcu exits halt mode. a recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the oscillator startup delay mask option. if the stop instruction has been selected by the stop mask option to put the mcu in halt mode, then the cop watchdog cannot be turned off inadvertently by a stop instruction. 6.4.4 data-retention mode in the data-retention mode, the mcu retains ram contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data retention feature allows the mcu to remain in a low-power consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in the data retention mode: 1. drive the reset pin to a logic zero. 2. lower the v dd voltage. the reset pin must remain low continuously during data retention mode. to take the mcu out of the data retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to a logic one.
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 77 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 7. parallel input/output 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . .80 7.3.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.3.4 port a external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.3.5 port a logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.4.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.4 port b logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.4.5 pb0, pbi, pb2, and pb3 logic . . . . . . . . . . . . . . . . . . . . . .87 7.4.6 pb4/an4/tcmp/cmp1 logic . . . . . . . . . . . . . . . . . . . . . . .89 7.4.7 pb5/sdo logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.4.8 pb6/sdi logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.9 pb7/sck logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 port c (mc68hc05jp6 only). . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.3 port c pulldown devices. . . . . . . . . . . . . . . . . . . . . . . . . .100 7.5.4 port c logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6 port transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 78 parallel input/output freescale semiconductor 7.2 introduction the mc68hc05jj6 has 14 bidirectional i/o pins which form two parallel i/o ports, a and b. the mc68hc05jp6 has 22 bidirectional i/o pins which form three parallel i/o ports, a, b and c. each i/o pin is programmable as an input or an output. the contents of the data direction registers determine the data direction of each of the i/o pins. all i/o pins have software programmable pulldown devices which can be enabled or disabled by the software pulldown inhibit mask option. 7.3 port a port a is a 6-bit, general-purpose bidirectional i/o port with these features: individual programmable pulldown devices high current sinking capability on all port a pins with a maximum of 15 ma per pin or a total of 40 ma for all six pins high current sourcing capability on all port a pins with a maximum of 5 ma per pin or a total of 20 ma for all six pins external interrupt capability (pins pa3?a0)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 79 non-disclosure agreement required 7.3.1 port a data register the port a data register contains a bit for each of the port a pins. when a port a pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port a pin is programmed to be an input, reading the port a data register returns the logic state of the pin. the upper two bits of the port a data register will always read as logical zeros. pa5?a0 ?port a data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in the port a data direction register (ddra). reset has no effect on port a data. $0000 bit 7 654321 bit 0 read: 0 0 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset alternate: kybd3 kybd2 kybd1 kybd0 = unimplemented figure 7-1. port a data register (porta)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 80 parallel input/output freescale semiconductor 7.3.2 data direction register a the contents of the port a data direction register (ddra) determine whether each port a pin is an input or an output. writing a logic one to a ddra bit enables the output buffer for the associated port a pin. a ddra bit set to a logic one also disables the pulldown device for that pin. writing a logic zero to a ddra bit disables the output buffer for the associated port a pin. the upper two bits always read as logical zeros. a reset initializes all ddra bits to logic zeros, configuring all port a pins as inputs and disabling the voltage comparators from driving pa4 or pa5. ddra5?dra0 ?port a data direction bits these read/write bits control port a data direction. reset clears the ddra5?dra0 bits. 1 = corresponding port a pin con?ured as output and pulldown device disabled 0 = corresponding port a pin con?ured as input $0004 bit 7 654321 bit 0 read: 0 0 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 = unimplemented figure 7-2. data direction register a (ddra)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 81 non-disclosure agreement required 7.3.3 pulldown register a all port a pins can have software programmable pulldown devices enabled or disabled by a mask option. when enabled these pulldowns can sink approximately 100 a. these pulldown devices are controlled by the write-only pulldown register a (pdra) shown in figure 7-3 . clearing the pdia5?dia0 bits in the pdra turns on the pulldown devices if the port a pin is an input. reading the pdra returns undefined results since it is a write-only register. on the mc68hc05jj6, the pdra contains two pulldown control bits (pdich and pdicl) for port c. reset clears the pdia5?dia0, pdich and pdicl bits, which turns on all the port a and port c pulldown devices. pdich ?upper port c pulldown inhibit bits (mc68hc05jp6) writing to this write-only bit controls the port c pulldown devices on the upper four bits (pc4:pc7). reading these pulldown register a bits returns undefined data. reset clears bit pdich. 1 = upper four port c pins pulldown devices turned off 0 = upper four port c pins pulldown devices turned on if pin has been programmed by the ddrc to be an input pdicl ?lower port c pulldown inhibit bits (mc68hc05jp6) writing to this write-only bit controls the port c pulldown devices on the lower four bits (pc0:pc3). reading these pulldown register a bits returns undefined data. reset clears bit pdicl. 1 = lower four port c pins pulldown devices turned off 0 = lower four port c pins pulldown devices turned on if pin has been programmed by the ddrc to be an input $0010 bit 7 654321 bit 0 read: write: pdich pdicl pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset: 00000000 = unimplemented figure 7-3. pulldown register a (pdra)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 82 parallel input/output freescale semiconductor pdia5?dia0 ?port a pulldown inhibit bits writing to these write-only bits controls the port a pulldown devices. reading these pulldown register a bits returns undefined data. reset clears bits pdia5?dia0. 1 = corresponding port a pin pulldown device turned off 0 = corresponding port a pin pulldown device turned on if pin has been programmed by the ddra to be an input 7.3.4 port a external interrupts a mask option enables the pa3?a0 pins to serve as external interrupt pins in addition to the irq pin. the active interrupt state for the pa3?a0 pins is a logic one or a rising edge. another mask option also determines whether external interrupt inputs are edge-sensitive only or both edge- and level-sensitive. port a interrupts are also interactive with each other and the irq pin as described in 4.6 external interrupts . note: when testing for external interrupts, the bih and bil instructions test the voltage on the irq pin, not the state of the internal irq signal. therefore, bih and bil cannot test the port a external interrupt pins. 7.3.5 port a logic when a pa0:pa5 pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. when a pa0:pa5 pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddr bit. figure 7-4 shows the i/o logic of pa0:pa5 pins of port a. the data latch can always be written, regardless of the state of its ddr bit. table 7-1 summarizes the operations of the port a pins.
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 83 non-disclosure agreement required figure 7-4. port a i/o circuit pax external interrupt request port a data register bit pax read $0004 write $0000 read $0000 write $0010 100 a pulldown device reset internal data bus 15 ma sink 5 ma source write $0004 data direction register a bit ddrax pulldown register a bit pdiax r r capability (pa0:pa3) pulldown inhibit mask option (enable = 0) table 7-1. port a pin functions port a pin(s) mask option pulldown inhibit port a porta access (pin or data register) result on port a pins pdian ddran* read write pulldown pin pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 0 0 0 pin data on pan in 0 1 0 pin data off pan in 1 x 0 pin data off pan in x x 1 data data off pan out * ddra can always be read or written. x = don? care
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 84 parallel input/output freescale semiconductor 7.4 port b port b is an 8-bit, general-purpose bidirectional i/o port with the following features: programmable pulldown devices pb0 through pb4 shared with the analog subsystem pb3 and pb4 shared with the 16-bit programmable timer pb4 can be driven directly by the output of comparator 1 pb5 through pb7 shared with the simple serial interface (siop) high current sinking capability to 15 ma on the pb4 pin high current sourcing capability to 5 ma on the pb4 pin 7.4.1 port b data register the port b data register contains a bit for each of the port b pins. when a port b pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port b pin is programmed to be an input, reading the port b data register returns the logic state of the pin. reset has no effect on port b data. pb0?b7 ?port b data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. $0001 bit 7 654321 bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset alternate: sck sdi sdo an4 an3 an2 an1 an0 alternate: sck sdi sdo tcmp tcap alternate: sck sdi sdo cmp1 tcap figure 7-5. port b data register (portb)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 85 non-disclosure agreement required 7.4.2 data direction register b the contents of the port b data direction register (ddrb) determine whether each port b pin is an input or an output. writing a logic one to a ddrb bit enables the output buffer for the associated port b pin. a ddrb bit set to a logic one also disables the pulldown device for that pin. writing a logic zero to a ddrb bit disables the output buffer for the associated port b pin. a reset initializes all ddrb bits to logic zeros, configuring all port b pins as inputs. ddrb7?drb0 ?port b data direction bits these read/write bits control port b data direction. reset clears the bits ddrb7?drb0. 1 = corresponding port b pin con?ured as output and pulldown device disabled 0 = corresponding port b pin configured as input $0005 bit 7 654321 bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 figure 7-6. data direction register b (ddrb)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 86 parallel input/output freescale semiconductor 7.4.3 pulldown register b all port b pins can have software programmable pulldown devices enabled or disabled by the software pulldown inhibit mask option. when enabled these pulldowns can sink approximately 100 a. these pulldown devices are controlled by the write-only pulldown register b (pdrb) shown in figure 7-7 . clearing the pdib7?dib0 bits in the pdrb turns on the pulldown devices if the port b pin is an input. reading the pdrb returns undefined results since it is a write-only register. reset clears the pdib7?dib0 bits, which turns on all the port b pulldown devices. pdib7?dib0 ?port b pulldown inhibit bits writing to these write-only bits controls the port b pulldown devices. reading these pulldown register b bits returns undefined data. reset clears bits pdib7?dib0. 1 = corresponding port b pin pulldown device turned off 0 = corresponding port b pin pulldown device turned on if pin has been programmed by the ddrb to be an input 7.4.4 port b logic all port b pins have the general i/o port logic similar to port a; but they also share this function with inputs or outputs from other modules, which are also attached to the pin itself or override the general i/o function. pb0, pb1, pb2, and pb3 simply share their inputs with another module. pb4, pb5, pb6, and pb7 will have their operation altered by outputs or controls from other modules. $0011 bit 7 654321 bit 0 read: write: pdib7 pdib6 pdib5 pdib4 pdib3 pdib2 pdib1 dib0 reset: 00000000 = unimplemented figure 7-7. pulldown register b (pdrb)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 87 non-disclosure agreement required 7.4.5 pb0, pbi, pb2, and pb3 logic the typical i/o logic shown in figure 7-8 is used for pb0, pb1, pb2, and pb3 pins of port b. when these port b pins are programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. when these port b pins are programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddrb bit. the operations of the pb0:pb3 pins are summarized in table 7-2 . figure 7-8. pb0:pb3 pin i/o circuit port bdata register bit pbx data direction register b bit ddrbx pulldown register b bit pdibx r r pbx analog subsystem, and programmable timer input capture read $0005 write $0001 read $0001 write $0011 100 a pulldown device reset internal data bus (pins pb0, pb1, pb2, pb3) write $0005 pulldown inhibit mask option (enable = 0)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 88 parallel input/output freescale semiconductor the pb0:pb3 pins share their inputs with another module. when using the other attached module, these conditions must be observed: 1. if the ddrb configures the pin as an output, then the port data register can provide an output which may conflict with any external input source to the other module. the pulldown device will be disabled in this case. 2. if the ddrb configures the pin as an input, then reading the port data register will return the state of the input in terms of the digital threshold for that pin. (analog inputs will default to logic states.) 3. if ddrb configures the pin as an input and the pulldown device is activated for a pin, it will also load the input to the other module. 4. if interaction between the port logic and the other module is not desired, the pin should be configured as an input by clearing the appropriate ddrb bit and disabling the input pulldown device by clearing the appropriate pdrb bit (or by disabling programmable pulldowns with a mask option).
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 89 non-disclosure agreement required 7.4.6 pb4/an4/tcmp/cmp1 logic the pb4/an4/tcmp/cmp1 pin can be used as a simple i/o port pin, be controlled by the olvl bit from the output compare function of the 16-bit programmable timer, or be controlled directly by the output of comparator 1 as shown in figure 7-9 . the pb4 data, the programmable timer olvl bit, and the output of comparator 1 are all ored together to drive the pin. also, the analog subsystem input channel 4 multiplexer is connected directly to this pin. the operations of the pb4 pin are summarized in table 7-2 . figure 7-9. pb4/an4/tcmp/cmp1 pin i/o circuit port bdata register bit pb4 data direction register b bit ddrb4 pulldown register b bit pdib4 r r pb4 analog subsystem input an4 and timer output compare read $0005 write $0001 read $0001 write $0011 100 a pulldown device reset internal data bus write $0005 an4 tcmp olvl cmp1 comparator 1 out timer output compare 15 ma sink 5 ma source capability pulldown inhibit mask option comp 1 output mask option (enable = 0) (enable = 1)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 90 parallel input/output freescale semiconductor when using the pb4/an4/tcmp/cmp1 pin, these interactions must be noted: 1. if the olvl timer output compare function is the required output function, then the ddrb4 bit must be set, the pb4 data bit must be cleared and the comparator output feature disabled by a mask option. the pb4/an4/tcmp/cmp1 pin becomes an output which follows the state of the olvl bit. the pulldown device will be disabled in this case. the analog subsystem would not normally use this pin as an analog input in this case. 2. if the pb4 data bit is the required output function, then the ddrb4 bit must be set, the olvl bit in the tcr must be cleared and the comparator output feature disabled by a mask option. the pulldown device will be disabled in this case. the analog subsystem would not normally use this pin as an analog input in this case. 3. if the comparator 1 output is the desired output function, then the pb4 data bit must be cleared, the ddrb4 bit must be set, the olvl bit in the tcr must be cleared, and the comparator output feature must be enabled by the analog options mask option. the pb4/an4/tcmp/cmp1 pin becomes an output which follows the state of the olvl bit. the pulldown device will be disabled in this case. the analog subsystem would not normally use this pin as an analog input in this case. 4. if the pb4 pin is to be an input to the analog subsystem or a digital input, then the ddrb4 bit must be cleared. in this case, the pb4 pin can still be read; but the voltage present will be returned as a binary value. depending on the external application, the pb4 pulldown may also be disabled by setting the pdib4 pulldown inhibit bit. in this case, both the digital and analog functions connected to this pin can be utilized. .
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 91 non-disclosure agreement required table 7-2. port b pin functions ?pb0:pb4 port b pin control bits portb access (pin or data register) result on port b pins comparator 1 timer mask option inhibit pull- down port b cmp1 coe1 mask option comp output olvl pdibn ddrbn* read write pulldown pin pb0 pb1 pb2 pb3 xxxx 0 0 0 pin data on pbn in 0 1 0 pin data off pbn in 1 x 0 pin data off pbn in x x 1 data data off pbn out pb4 xxxx 0 0 0 pin data on pb4 in 0 1 0 pin data off pb4 in 1 x 0 pin data off pb4 in x x 0 0 x x 1 data data off pb4 out x 0 1 0 x x 1 data data off pb4 out 0110xx 1datadataoff pb4 out x x x 1 x x 1 1 data off 1 1 1 1 x x x 1 1 data off 1 * ddrb can always be read or written. x = don? care
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 92 parallel input/output freescale semiconductor 7.4.7 pb5/sdo logic the pb5/sdo pin can be used as a simple i/o port pin or be controlled by the siop serial interface as shown in figure 7-10 . the operations of the pb5 pin are summarized in table 7-3 . figure 7-10 . pb5/sdo pin i/o circuit data direction register b bit ddrb5 port b data register bit pb5 pulldown register b bit pdib5 r r pb5 read $0005 write $0001 read $0001 write $0011 100 a pulldown device reset internal data bus write $0005 sdo serial enable (spe) serial data out (sdo) v dd pulldown inhibit mask option (enable = 0)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 93 non-disclosure agreement required when using the pb5/sdo pin, these interactions must be noted: 1. if the siop function is required, then the spe bit in the scr must be set. this causes the pb5/sdo pin buffer to be enabled and to be driven by the serial data output (sdo) from the siop. the pulldown device will be disabled in this case. 2. if the siop function is in control of the pb5/sdo pin, the ddrb5 and pb5 data register bits are still accessible to the cpu and can be altered or read without affecting the siop functionality. however, if the ddrb5 bit is cleared, reading the pb5 data register will return the current state of the pb5/sdo pin. 3. if the siop function is terminated by clearing the spe bit in the scr, then the last conditions stored in the ddrb5, pdib5, and pb5 register bits will then control the pb5/sdo pin. 4. if the pb5/sdo pin is to be a digital input, then both the spe bit in the scr and the ddrb5 bit must be cleared. depending on the external application, the pulldown device may also be disabled by setting the pdib5 pulldown inhibit bit. 5. if the pb5/sdo pin is to be a digital output, then the spe bit in the scr must be cleared and the pdib5 bit must be set. the pulldown device will be disabled in this case.
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 94 parallel input/output freescale semiconductor 7.4.8 pb6/sdi logic the pb6/sdi pin can be used as a simple i/o port pin or be controlled by the siop serial interface as shown in figure 7-11 . the operations of pb6/sdi pin are summarized in table 7-3 . figure 7-11. pb6/sdi pin i/o circuit data direction register b bit ddrb6 port b data register bit pb6 pulldown register b bit pdib6 r r pb6 read $0005 write $0001 read $0001 write $0011 100 a pulldown device reset internal data bus write $0005 sdi serial enable (spe) serial data in (sdi) pulldown inhibit mask option (enable = 0)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 95 non-disclosure agreement required when using the pb6/sdi pin, these interactions must be noted: 1. if the siop function is required, then the spe bit in the scr must be set. this causes the pb6/sdi pin buffer to be disabled to allow the pb6/sdi pin to act as an input that feeds the serial data input (sdi) of the siop. the pulldown device is disabled in this case. 2. if the siop function is in control of the pb6/sdi pin, the ddrb6 and pb6 data register bits are still accessible to the cpu and can be altered or read without affecting the siop functionality. however, if the ddrb6 bit is cleared, reading the pb6 data register will return the current state of the pb6/sdi pin. 3. if the siop function is terminated by clearing the spe bit in the scr, then the last conditions stored in the ddrb6, pdib6, and pb6 register bits will then control the pb6/sdi pin. 4. if the pb6/sdi pin is to be a digital input, then both the spe bit in the scr and the ddrb6 bit must be cleared. depending on the external application, the pulldown device may also be disabled by setting the pdib6 pulldown inhibit bit. 5. if the pb6/sdi pin is to be a digital output, then the spe bit in the scr must be cleared and the ddrb6 bit must be set. the pulldown device will be disabled in this case.
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 96 parallel input/output freescale semiconductor 7.4.9 pb7/sck logic the pb7/sck pin can be used as a simple i/o port pin or be controlled by the siop serial interface as shown in figure 7-12 . the operations of the pb7/sck pin are summarized in table 7-3 . figure 7-12. pb7/sck pin i/o circuit data direction register b bit ddrb7 port b data register bit pb7 pulldown register b bit pdib7 r r pb7 read $0005 write $0001 read $0001 write $0011 100 a pulldown device reset internal data bus write $0005 sck serial enable (spe) clock source (mstr) serial data clock (sck) pulldown inhibit mask option (enable = 0)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 97 non-disclosure agreement required when using the pb7/sck pin, these interactions must be noted: 1. if the siop function is required, then the spe bit in the scr must be set. this causes the pb7/sck pin buffer to be controlled by the mstr control bit in the scr. the pulldown device is disabled in these cases. a. if the mstr bit is set, then the pb7/sck pin buffer will be enabled and driven by the serial data clock (sck) from the siop. b. if the mstr bit is clear, then the pb7/sck pin buffer will be disabled, allowing the pb7/sck pin to drive the serial data clock (sck) into the siop. 2. if the siop function is in control of the pb7/sck pin, the ddrb7 and pb7 data register bits are still accessible to the cpu and can be altered or read without affecting the siop functionality. however, if the ddrb7 bit is cleared, reading the pb7 data register will return the current state of the pb7/sck pin. 3. if the siop function is terminated by clearing the spe bit in the scr, then the last conditions stored in the ddrb7, pdib7, and pb7 register bits will then control the pb7/sck pin. 4. if the pb7/sck pin is to be a digital input, then both the spe bit in the scr and the ddrb7 bit must be cleared. depending on the external application, the pulldown device may also be disabled by setting the pdib7 pulldown inhibit bit. 5. if the pb7/sck pin is to be a digital output, then the spe bit in the scr must be cleared and the ddrb7 bit must be set. the pulldown device will be disabled when the pin is set as an output.
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 98 parallel input/output freescale semiconductor table 7-3. port b pin functions ?pb5:pb7 port b pin control bits portb access (pin or data register) result on port b pins siop mask option inhibit pull- down port b spe mstr pdibn ddrbn* read write pulldown pin pb5 0x 0 0 0 pin data on pb5 in 0 1 0 pin data off pb5 in 1 x 0 pin data off pb5 in x x 1 data data off pb5 out 1xxx 0 sdo data off sdo out 1 data data off sdo out pb6 0x 0 0 0 pin data on pb6 in 0 1 0 pin data off pb6 in 1 x 0 pin data off pb6 in x x 1 data data off pb6 out 1xxx 0 sdi data off sdi in 1 data data off sdi in pb7 0x 0 0 0 pin data on pb7 in 0 1 0 pin data off pb7 in 1 x 0 pin data off pb7 in x x 1 data data off pb7 out 1 0xx 0 sck data off sck in 1 data data off sck in 1xx 0 sck data off sck out 1 data data off sck out * ddrb can always be read or written. x = don? care
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 99 non-disclosure agreement required 7.5 port c (mc68hc05jp6 only) port c is an 8-bit, general-purpose bidirectional i/o port with individual programmable pulldown devices. it is only available on the 28-pin mc68hc05jp6 device. port c has these features: independent high and low nibble programmable pulldown devices high-current sinking capability on all port c pins with a maximum of 15 ma per pin or a total of 60 ma for all eight pins high-current sourcing capability on all port c pins with a maximum of 5 ma per pin or a total of 30 ma for all eight pins 7.5.1 port c data register the port c data register contains a bit for each of the port c pins. when a port c pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port c pin is programmed to be an input, reading the port c data register returns the logic state of the pin. pc7?c0 ?port c data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in the port c data direction register (ddrc). reset has no effect on port c data. note: for 20-pin devices, port c pins are not available. however, port c logic is present on the mcu. therefore, port c must be enabled as an output or pulldowns must be enabled. this is to prevent floating input pins. $0002 bit 7 654321 bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset figure 7-13. port c data register (portc)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 100 parallel input/output freescale semiconductor 7.5.2 data direction register c the contents of the port c data direction register (ddrc) determine whether each port c pin is an input or an output. writing a logic one to a ddrc bit enables the output buffer for the associated port c pin. a ddrc bit set to a logic one also disables the pulldown device for that pin. writing a logic zero to a ddrc bit disables the output buffer for the associated port c pin. a reset initializes all ddrc bits to logic zeros, configuring all port c pins as inputs. ddrc7?drc0 ?port c data direction bits these read/write bits control port c data direction. reset clears the ddrc7?drc0 bits. 1 = corresponding port c pin con?ured as output and pulldown device disabled 0 = corresponding port c pin con?ured as input 7.5.3 port c pulldown devices all port c pins can have software programmable pulldown devices enabled or disabled by the software pulldown inhibit mask option. when enabled these pulldowns can sink approximately 100 a. these pulldown devices are controlled by the write-only pulldown register a (pdra) shown in figure 7-3 . pdich controls the upper four pins (pc7:pc4) and pdicl controls the lower four pins (pc3:pc0). clearing the pdich or pdicl bits in the pdra turns on the pulldown devices if the port c pin is an input. reading the pdra returns undefined results since it is a write-only register. reset clears the pdich and pdicl bits, which turns on all the port c pulldown devices. $0006 bit 7 654321 bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 figure 7-14. data direction register c (ddrc)
parallel input/output mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor parallel input/output 101 non-disclosure agreement required 7.5.4 port c logic figure 7-15 shows the i/o logic of port c. when a port c pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. when a port c pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddr bit. table 7-4 summarizes the operations of the port c pins. figure 7-15. port c i/o circuit pcx port c data register bit pcx read $0006 write $0002 read $0002 write $0010 100 a pulldown device reset internal data bus write $0006 data direction register c bit ddrcx pulldown register a bit pdicx r r 15 ma sink 5 ma source capability pulldown inhibit mask option (enable = 0)
non-disclosure agreement required parallel input/output general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 102 parallel input/output freescale semiconductor 7.6 port transitions glitches and temporary floating inputs can occur if the control bits regarding each port i/o pin are not performed in the correct sequence. do not use read-modify-write instructions on pulldown register a or b. avoid glitches on port pins by writing to the port data register before changing data direction register bits from a logic zero to a logic one. avoid a floating port input by clearing its pulldown register bit before changing its data direction register bit from a logic one to a logic zero. a mask option turns off all port pulldown devices and disables software control of the pulldown devices. reset has no effect on the pulldown devices if they are not selected by mask option. table 7-4. port c pin functions (mc68hc05jp6) port c pin(s) control bits portc access (pin or data register) result on port c pins mask option pull- down inhibit port c pdich pdicl ddrcn* read write pulldown pin low nibble pc0 pc1 pc2 pc3 0 x 0 0 pin data on pcn in 0 x 1 0 pin data off pcn in 1 x x 0 pin data off pcn in x x x 1 data data off pcn out high nibble pc4 pc5 pc6 pc7 0 0 x 0 pin data on pcn in 0 1 x 0 pin data off pcn in 1 x x 0 pin data off pcn in x x x 1 data data off pcn out * ddrc can always be read or written. x = don? care
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 103 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 8. analog subsystem 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.3 analog multiplex register . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.4 analog control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.5 analog status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.6 a/d conversion methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.7 voltage measurement methods . . . . . . . . . . . . . . . . . . . . . . .128 8.7.1 absolute voltage readings . . . . . . . . . . . . . . . . . . . . . . . .129 8.7.1.1 internal absolute reference. . . . . . . . . . . . . . . . . . . . . .129 8.7.1.2 external absolute reference . . . . . . . . . . . . . . . . . . . . .130 8.7.2 ratiometric voltage readings. . . . . . . . . . . . . . . . . . . . . .131 8.7.2.1 internal ratiometric reference . . . . . . . . . . . . . . . . . . .131 8.7.2.2 external ratiometric reference . . . . . . . . . . . . . . . . . . .131 8.8 voltage comparator features . . . . . . . . . . . . . . . . . . . . . . . .133 8.9 current source features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.10 internal temperature sensing diode features. . . . . . . . . . . .134 8.11 sample and hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.12 port b interaction with analog inputs . . . . . . . . . . . . . . . . . . .135 8.13 port b pins as inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.14 port b pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.15 noise sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.2 introduction the analog subsystem of the mc68hc05jj6/mc68hc05jp6 is based on two on-chip voltage comparators and a selectable current charge/discharge function as shown in figure 8-1 .
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 104 analog subsystem freescale semiconductor figure 8-1. analog subsystem block diagram analog interrupt pb0 v dd tof ocf an0 charge current chg + pb1 an1 v dd pb2 an2 pb3 an3 pb4 an4 inv comp2 portb logic mux4 mux3 mux1 mux2 sample portb logic portb logic portb logic portb logic i chg hold inv dhold vref mux4 mux3 mux2 mux1 i dischg 2 to 1 mux 16-bit prog. analog tcap internal hc05 bus cmp2 cmp1 cap 80 k 80 k tcap tcmp mux4 mux3 mux2 channel select bus cp1en mux1 vref isen cp2en analog control register (acr) icen cpie cp1en cp2en mux register (amux) cpf1 analog status register (asr) cpf2 pb3/an3/tcap timer + inv comp1 atd2 atd1 icf control logic v dd temperature diode internal vref v ss denotes internal analog v ss v ss + - v aoff $001d $001e $0003 voff v offset 100 mv offset + comparator input select and sample control port b control coe1 mask mask option option logic
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 105 non-disclosure agreement required this configuration provides several features: two (2) independent voltage comparators with external access to both inverting and non-inverting inputs one voltage comparator can be connected as a single-slope a/d and the other connected as a single-voltage comparator. the possible single-slope a/d connection provides these features: a/d conversions can use v dd or an external voltage as a reference with software used to calculate ratiometric or absolute results channel access of up to four inputs via multiplexer control with independent multiplexer control allowing mixed input connections access to v dd and v ss for calibration divide by 2 to extend input voltage range each comparator can be inverted to calculate input offsets internal sample and hold capacitor direct digital output of comparator 1 to the pb4 pin voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the unknown input voltage being measured. the beginning of the a/d conversion time can be started by these means: output compare from the 16-bit programmable timer timer overflow from the 16-bit programmable timer direct software control via a register bit the end of the a/d conversion time can be captured by these means: input capture in the 16-bit programmable timer interrupt generated by the comparator output software polling of the comparator output using software loop time
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 106 analog subsystem freescale semiconductor 8.3 analog multiplex register the analog multiplex register (amux) controls the general interconnection and operation. the control bits in the amux are shown in figure 8-2 . hold, dhold these read/write bits control the source connection to the negative input of voltage comparator 2 shown in figure 8-3 . this allows the voltage on the internal temperature sensing diode, the channel selection bus, or the 1:2 divided channel selection bus to charge the internal sample capacitor and to also be presented to comparator 2. the decoding of these sources is given in table 8-1 . during the hold case when both the hold and dhold bits are clear, the voff bit in the analog status register (asr) can offset the v ss reference on the sample capacitor by approximately 100 mv. this offset source is bypassed whenever the sample capacitor is being charged with either the hold or dhold bit set. the voff bit must be enabled by the analog options mask option. during a reset the hold bit is set and the dhold bit is cleared, which connects the internal sample capacitor to the channel selection bus. and since a reset also clears the mux1:mux4 bits, the channel selection bus will be connected to v ss and the internal sample capacitor will be discharged to v ss following the reset. note: when sampling a voltage for later conversion, the hold and dhold bits should be cleared before making any changes in the mux channel selection. if the mux channel and the hold/dhold are changed on the same write cycle to the amux register, the sampled voltage may be altered during the channel switching. $0003 bit 7 654321 bit 0 read: hold dhold inv vref mux4 mux3 mux2 mux1 write: reset: 10000000 figure 8-2. analog multiplex register (amux)
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 107 non-disclosure agreement required figure 8-3. comparator 2 input circuit + comp2 sample hold dhold cap 80 k 80 k temperature diode internal voff v ss offset + mask option channel pb0 selection bus v dd (enable = 1) table 8-1. comparator 2 input sources case hold (amux) dhold (amux) mask option analog options voff (asr) voltage offset source to negative input of comparator 2 hold sample voltage 00 0x no sample capacitor connected to comparator 2 negative input; very low leakage current. 10 11yes sample capacitor connected to comparator 2 negative input; bottom of capacitor offset from v ss by approximately 100 mv, very low leakage current. divided input 01xxno signal on channel selection bus is divided by 2 and connected to sample capacitor and comparator 2 negative input direct input 10xxno signal on channel selection bus is connected directly to sample capacitor and comparator 2 negative input. internal temperature diode 11xxno internal temperature sensing diode connected directly to sample capacitor and comparator 2 negative input. x = don? care
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 108 analog subsystem freescale semiconductor inv this is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage comparators. this bit allows voltage comparisons to be made with both polarities and then averaged together by taking the sum of the two readings and then dividing by 2 (logical shift right). the polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while also inverting the comparator output. this interchange does not alter the action of the voltage comparator output with respect to its port pins. that is, the output will only go high if the voltage on the positive input (pb2 pin for comparator 1 and pb0 pin for comparator 2) is above the voltage on the respective negative input (pb3 pin for comparator 1 and pb1 pin for comparator 2). this is shown schematically in figure 8-4 . this bit is cleared by a reset of the device. 1 = voltage comparators internally inverted 0 = voltage comparators not internally inverted figure 8-4. inv bit action note: the effect of changing the state of the inv bit is to only change the polarity of the input offset voltage. it does not change the output phase of the cpf1 or cpf2 flags with respect to the external port pins. v v+ inv = 0 + comp v io rise when v+ > v inv = 1 v+ v + comp v io rise when v+ > v
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 109 non-disclosure agreement required note: either comparator may generate an output flag when the inputs are exchanged due to a change in the state of the inv bit. it is therefore recommended that the inv bit not be changed while waiting for a comparator flag. further, any changes to the state of the inv bit should be followed by writing a logical one to both the cpfr1 and cpfr2 bits to clear any extraneous cpf1 or cpf2 flags that may have occurred. vref this read/write bit connects the channel select bus to v dd for making a reference voltage measurement. it cannot be selected if any of the other input sources to the channel select bus are selected as shown in table 8-2 . this bit is cleared by a reset of the device. 1 = channel select bus is connected to v dd if all mux1:mux4 are cleared. 0 = channel select bus cannot be connected to v dd . mux1:mux4 these are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator 2 for purposes of making a voltage measurement. they can be selected individually or combined with any of the other input sources to the channel select bus as shown in table 8-2 . note: the v aoff voltage source shown in figure 8-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single v ss pin. this offset raises the internal v ss reference (av ss ) in the analog subsystem with respect to the external v ss pin. turning on the v ss mux to the channel select bus connects it to this internal av ss reference line. when making a/d conversions, this av ss offset gets placed on the external ramping capacitor since the discharge device on the pb0/an0 pin discharges the external capacitor to the internal av ss line. under these circumstances, the positive input (+) to comparator 2 will always be higher than the negative input (? until the negative input reaches the av ss offset voltage plus any offset in comparator 2. therefore, input voltages cannot be resolved if they are less than the sum of the av ss offset and the comparator offset because they will always yield a low output from the comparator.
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 110 analog subsystem freescale semiconductor table 8-2. channel select bus combinations analog multiplex register channel select bus connected to: vref mux4 mux3 mux2 mux1 v dd pb4/an4/ tcmp pb3/an3/ tcap pb2/an2 pb1/an1 v ss 00000- - -- - - - - - - - - - - -on x0001- - -- - - - - - - - - on- - - x0010- - -- - - - - - on - - -- - - x0011- - -- - - - - - on on- - - x0100- - -- - - on - - - - - -- - - x0101- - -- - - on - - - on- - - x0110- - -- - - on on - - -- - - x0111- - -- - - on on on- - - x1000- - -on - - - - - - - - -- - - x1001- - -on - - - - - - on- - - x1010- - -on - - - on - - -- - - x1011- - -on - - - on on- - - x1100- - -on on - - - - - -- - - x1101- - -on on - - - on- - - x1110- - -on on on - - -- - - x1111- - -on on on on- - - 10000on- - - - - - - - - - - -- - - x = don? care - - - = high impedance
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 111 non-disclosure agreement required 8.4 analog control register the analog control register (acr) controls the power-up, interrupt, and flag operation. the analog subsystem draws about 500 a of current while it is operating. the resulting power consumption can be reduced by powering down the analog subsystem when not in use. this can be done by clearing three enable bits (isen, cp1en, and cp2en) in the acr at $001d. since these bits are cleared following a reset, the voltage comparators and the charge current source will be powered down following a reset of the device. the control bits in the acr are shown in figure 8-5 . all the bits in this register are cleared by a reset of the device. chg the chg enable bit allows direct control of the charge current source and the discharge device; and also reflects the state of the discharge device. this bit is cleared by a reset of the device. 1 = if the isen bit is also set, the charge current source is sourcing current out of the pb0/an0 pin. writing a logical one enables the charging current out of the pb0/an0 pin. 0 = the discharge device is sinking current into the pb0/an0 pin. writing a logical zero disables the charging current and enables the discharging current into the pb0/an0 pin, if the isen bit is also set. atd1:atd2 the atd1:atd2 enable bits select one of the four operating modes used for making a/d conversions via the single-slope method. these four modes are given in table 8-3 . these bits have no effect if the isen enable bit is cleared. these bits are cleared by a reset of the device and thereby return the analog subsystem to the manual a/d conversion method. $001d bit 7 654321 bit 0 read: chg atd2 atd1 icen cpie cp2en cp1en isen write: reset: 00000000 figure 8-5. analog control register (acr)
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 112 analog subsystem freescale semiconductor table 8-3. a/d conversion options a/d option mode charge control a/d options current flow to/from pb0/an0 isen atd2 atd1 chg disabled current source and discharge disabled 0 x x x current control disabled, no source or sink current 0 manual charge and discharge 1000 begin sinking current when the chg bit is cleared and continue to sink current until the chg bit is set. 1001 begin sourcing current when the chg bit is set and continue to source current until the chg bit is cleared. 1 manual charge and automatic discharge 1010 begin sinking current when the chg bit is cleared and continue to sink current until the chg bit is set. (the chg bit is cleared by writing a logical zero to it or when the cpf2 ?g bit is set.) 1011 begin sourcing current when the chg bit is set; and continue to source current until the chg bit is cleared. (the chg bit is set by writing a logical one to it or cleared when the cpf2 ?g bit is set.) 2 automatic charge and discharge (tof?cf) synchronized to timer 1100 the chg bit remains cleared until the next timer tof occurs. 1101 the chg bit remains set until the next timer icf occurs. 3 automatic charge and discharge (ocf?cf) synchronized to timer 1110 the chg bit remains cleared until the next timer ocf occurs. 1111 the chg bit remains set until the next timer icf occurs. x = don? care
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 113 non-disclosure agreement required icen this is a read/write bit that enables a voltage comparison to trigger the input capture register of the programmable timer when the cpf2 flag bit is set. therefore, an a/d conversion could be started by receiving an ocf or tof from the programmable timer and then terminated when the voltage on the external ramping capacitor reaches the level of the unknown voltage. the time of termination will be stored in the 16-bit buffer located at $0014 and $0015. this bit is automatically set whenever mode 2 or mode 3 is selected by setting the atd2 control bit. this bit is cleared by a reset of the device. 1 = connects the cpf2 flag bit to the timer input capture register 0 = connects the pb3/an3 pin to the timer input capture register note: for the input capture to occur when the output of comparator 2 goes high, the iedg bit in the tcr must also be set. when the icen bit is set, the input capture function of the programmable timer is not connected to the pb3/an3/tcap pin but is driven by the cpf2 output flag from comparator 2. to return to capturing times from external events, the icen bit must first be cleared before the timed event occurs. cpie this is a read/write bit that enables an analog interrupt when either of the cpf1 or cpf2 flag bits is set to a logical one. this bit is cleared by a reset of the device. 1 = enables analog interrupts when comparator flag bits are set 0 = disables analog interrupts when comparator flag bits are set note: if both the icen and cpie bits are set, they will both generate an interrupt by different paths. one will be the programmable timer interrupt due to the input capture; and the other will be the analog interrupt due to the output of comparator 2 going high. in this case, the input capture interrupt will be entered first due to its higher priority. the analog interrupt will then need to be serviced even if the comparator 2 output has been reset or the input capture flag (icf) has been cleared.
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 114 analog subsystem freescale semiconductor cp2en the cp2en enable bit controls power to voltage comparator 2 in the analog subsystem. powering down a comparator will drop the supply current by about 100 a. this bit is cleared by a reset of the device. 1 = writing a logical one powers up voltage comparator 2. 0 = writing a logical zero powers down voltage comparator 2. note: voltage comparators power up slower than digital logic; and their outputs may go through indeterminate states which might set their respective flags (cpf1, cpf2). it is therefore recommended to power up the charge current source first (isen); then to power up any comparators, and finally clear the flag bits by writing a logic one to the respective cpfr1 or cpfr2 bits in the acr. cp1en the cp1en enable bit will power down the voltage comparator 1 in the analog subsystem. powering down a comparator will drop the supply current by about 100 a. this bit is cleared by a reset of the device. 1 = writing a logical one powers up voltage comparator 1. 0 = writing a logical zero powers down voltage comparator 1. isen the isen enable bit will power down the charge current source and disable the discharge device in the analog subsystem. powering down the current source will drop the supply current by about 200 a. this bit is cleared by a reset of the device. 1 = writing a logical one powers up the ramping current source and enables the discharge device on the pb0/an0 pin. 0 = writing a logical zero powers down the ramping current source and disables the discharge device on the pb0/an0 pin. note: the analog subsystem has support circuitry which draws about 80 aof current. this current will be powered down if both comparators and the charge current source are powered down (isen, cp1en, and cp2en all cleared). powering up either comparator or the charge current source will activate the support circuitry.
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 115 non-disclosure agreement required 8.5 analog status register the analog status register (asr) contains status and control of the comparator flag bits. these bits in the asr are shown in figure 8-6 . all the bits in this register are cleared by a reset of the device. cpf2 this read-only flag bit is edge sensitive to the rising output of comparator 2. it is set when the voltage on the pb0/an0 pin rises above the voltage on the sample capacitor which creates a positive edge on the output of comparator 2, regardless of the state of the inv bit in the amux register. this bit is reset by writing a logical one to the cpfr2 reset bit in the asr. this bit is cleared by a reset of the device. 1 = a positive transition on the output of comparator 2 has occurred since the last time the cpf2 flag has been cleared. 0 = a positive transition on the output of comparator 2 has not occurred since the last time the cpf2 flag has been cleared. cpf1 this read-only flag bit is edge sensitive to the rising output of comparator 1. it is set when the voltage on the pb2/an2 pin rises above the voltage on the pn3/an3/tcap pin which creates a positive edge on the output of comparator 1, regardless of the state of the inv bit in the amux register. this bit is reset by writing a logical one to the cpfr1 reset bit in the asr. this bit is cleared by a reset of the device. 1 = a positive transition on the output of comparator 1 has occurred since the last time the cpf1 flag has been cleared. 0 = a positive transition on the output of comparator 1 has not occurred since the last time the cpf1 flag has been cleared. $001e bit 7 654321 bit 0 read: cpf2 cpf1 0 0 coe1 voff cmp2 cmp1 write: cpfr2 cpfr1 r reset: 00000000 = unimplemented r = reserved figure 8-6. analog status register (asr)
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 116 analog subsystem freescale semiconductor cpfr2 writing a logical one to this write-only flag clears the cpf2 flag in the asr. writing a logical zero to this bit has no effect. reading the cpfr2 bit will return a logical zero. by default, this bit looks cleared following a reset of the device. 1 = clears the cpf2 flag bit 0 = no effect cpfr1 writing a logical one to this write-only flag clears the cpf1 flag in the asr. writing a logical zero to this bit has no effect. reading the cpfr1 bit will return a logical zero. by default, this bit looks cleared after a reset of the device. 1 = clears the cpf1 flag bit 0 = no effect note: the cpfr1 and cpfr2 bits should be written with logical ones following a power up of either comparator. this will clear out any latched cpf1 or cpf2 flag bits which might have been set during the slower power up sequence of the analog circuitry. if both inputs to a comparator are above the maximum common-mode input voltage (v dd ?.5 v) the output of the comparator is indeterminate and may set the comparator flag. applying a reset to the device may only temporarily clear this flag as long as both inputs of a comparator remain above the maximum common-mode input voltages. voff this read-write bit controls the addition of an offset voltage to the bottom of the sample capacitor. it is not active unless selected by a mask option. any reads of the voff bit location return a logical zero if the analog options mask option is disabled. during the time that the sample capacitor is connected to an input (either hold or dhold set), the bottom of the sample capacitor is connected to v ss . the voff bit is cleared by a reset of the device. 1 = enable approximately 100-mv offset to be added to the sample voltage when both the hold and dhold control bits are cleared. 0 = connect the bottom of the sample capacitor to v ss .
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 117 non-disclosure agreement required coe1 this read-write bit controls the output of comparator 1 to the pb4 pin. it is not active unless enabled by mask option. any reads of the coe1 bit location return a logical zero if the analog options mask option is not selected. the coe1 bit is cleared by a reset of the device. 1 = enables the output of comparator 1 to be ored with the pb4 data bit and olvl bit, if the ddrb4 bit is also set 0 = disables the output of comparator 1 from affecting the pb4 pin cmp2 this read-only bit shows the state of comparator 2 during the time that the bit is read. this bit is, therefore, the current state of the comparator without any latched history. the cmp2 bit will be high if the voltage on the pb0/an0 pin is greater than the voltage on the pb1/an1 pin, regardless of the state of the inv bit in the amux register. since a reset disables comparator 2, this bit returns a logical zero following a reset of the device. 1 = voltage on the positive input on comparator 2 higher than the voltage on the negative input of comparator 2 0 = voltage on the positive input on comparator 2 lower than the voltage on the negative input of comparator 2 cmp1 this read-only bit shows the state of comparator 1 during the time that the bit is read. this bit is, therefore, the current state of the comparator without any latched history. the cmp1 bit will be high if the voltage on the pb2/an2 pin is greater than the voltage on the pb3/an3/tcap pin, regardless of the state of the inv bit in the amux register. since a reset disables comparator 1, this bit returns a logical zero following a reset of the device. 1 = voltage on the positive input on comparator 1 higher than the voltage on the negative input of comparator 1 0 = voltage on the positive input on comparator 1 lower than the voltage on the negative input of comparator 1
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 118 analog subsystem freescale semiconductor 8.6 a/d conversion methods the control bits in the acr provide various options to charge or discharge current through the pb0/an0 pin in order to perform single- slope a/d conversions using an external capacitor from the pb0/an0 pin to v ss as shown in figure 8-7 . the various a/d conversion triggering options are given in table 8-3 . figure 8-7. single-slope a/d conversion method the top three bits of the acr control the charging and discharging current into or out of the pb0/an0 pin. these three bits will have no effect on the pb0/an0 pin if the isen enable bit is cleared. any clearing of the isen bit will immediately disable both the charge current source and the discharge device. since all these bits and the isen bit are unknown voltage on (? input charge time to match unknown discharge time to reset capacitor voltage on capacitor connected to (+) input maximum charge time to v dd ?.5 vdc v dd ?.5 vdc cx v x i v dd + 5 v ramp cap v ss pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 unknown or reference mc68hc05jj6 charge time = mc68hc05jp6 signals
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 119 non-disclosure agreement required cleared when the device is reset, the mc68hc05jj6/mc68hc05jp6 starts with the charge and discharge function disabled. the length of time required to reach the maximum voltage to be measured and the speed of the time counting mechanism will determine the resolution of the reading. the time to ramp the external capacitor voltage to match the maximum voltage is dependent on: charging current to external capacitor value of the external capacitor clock rate for timing function any prescaling of the clock to the timing function desired resolution the charging behavior is described by the general equation: t chg = c ext x v x / i chg where: t chg = charge time (seconds) c ext = capacitance ( f) v x = unknown voltage (volts) i chg = charge current ( a) since the mcu can measure time in a variety of ways, the resolution of the conversion will depend on the length of the time-keeping function and its prescaling to the oscillator frequency (f osc ). therefore, the charge time also equals: t chg = p x n / f osc where: p = prescaler value ( 2, 4, 8, etc.) n = number of counts during charge time f osc = oscillator clock frequency (hz) note: noise on the system ground or the external ramping capacitor can cause the comparator to trip prematurely. therefore, in any given application it is best to use the fastest possible ramp rate (shortest charge time).
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 120 analog subsystem freescale semiconductor the above two equations for the charge time, t chg , can be combined to form this expression for the full scale count (n fs ) of the measured time versus the full scale unknown voltage (v fs ): n fs = c ext x v fs x f osc / (p x i chg ) since a given timing method has a fixed charge current and prescaler, then the variation in the resultant count for a given unknown voltage is mainly dependent on the operating frequency and the capacitance value used. the desired external capacitance for a given voltage range, f osc , conversion method, and resolution is defined as: c ext = n fs x p x i chg / (v fs x f osc ) note: the value of any capacitor connected directly to the pb0/an0 pin should be limited to less than 2 microfarads. larger capacitances will create high discharge currents which may damage the device or create signal noise. note: the desired type of capacitor for the ramp capacitor is any of the ?oly film types which have both low leakage and low dielectric absorption (somtimes referred to as memory behavior). low-cost monolithic ceramics are good for bypass use, but have high dielectric absorption which makes them less desirable for an integration or storage application. tantalum or aluminum electrolytics have high dielectric absorption and too much leakage, as well. for integration or storage capacitors use capacitors which have a dielectric absorption of less than 0.01%. the full scale voltage range for a given capacitance, f osc , conversion method, and resolution is defined as: v fs = n fs x p x i chg / (c ext x f osc ) once charged to a given voltage, a finite amount of time will be required to discharge the capacitor back to its start voltage at v ss . this discharge time will be solely based on the value of capacitance used and the sinking current of the internal discharge device. to allow a reasonable time for the capacitor to return to v ss levels, the discharge time should last about 10 milliseconds per microfarad of capacitance attached to the pb0 pin. if the total charge/discharge cycle time is critical, then the discharge time should be at least 1/10 of the most recent charge time.
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 121 non-disclosure agreement required shorter discharge times may be used if lesser accuracy in the voltage measurement is acceptable. note: sufficient time should be allowed to discharge the external capacitor or subsequent charge times will be shortened with resultant errors in timing conversion. table 8-4 gives the range of values of each parameter in the a/d timing conversion; and table 8-5 gives some a/d conversion examples for several bit resolutions. the mode selection bits in the acr allow four methods of single-slope a/d conversion. each of these methods is shown in the following figures using the signal names and parameters given in table 8-4 . manual start and stop (mode 0) figure 8-8 manual start and automatic discharge (mode 1) figure 8-9 automatic start and stop from tof to icf (mode 2) figure 8-10 automatic start and stop from ocf to icf (mode 3) figure 8-11
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 122 analog subsystem freescale semiconductor table 8-4. a/d conversion parameters name function min typ max units v x unknown voltage on channel selection bus v ss ? dd ?.5 v v cap charging voltage on external capacitor v ss ? dd ?.5 v v max maximum charging voltage on external capacitor v dd ?.5 v i chg charging current on external ramping capacitor v dd = 3 vdc v dd = 5 vdc refer to 13.10 analog subsystem characteristics (5.0 vdc) and 13.11 analog subsystem characteristics (3.0 vdc) a i dis discharge current on external ramping capacitor refer to 13.10 analog subsystem characteristics (5.0 vdc) and 13.11 analog subsystem characteristics (3.0 vdc) ma t chg time to charge external capacitor (100 khz < f osc < 4.0 mhz) 4-bit result 6-bit result 8-bit result 10-bit result 12-bit result 0.032 0.128 0.512 2.048 8.192 0.128 0.512 2.048 8.196 32.768 2.56 10.24 40.96 120 (1) 120 (1) ms ms ms ms ms t dis time to discharge external capacitor, c ext 5 10 ms / f c ext capacitance of external ramping capacitor 0.0001 0.1 2.0 (2) f n number of counts for i chg to charge c ext to v x 1 1024 65536 counts p prescaler into timing function ( p) using core timer using 16-bit programmable timer using software loops 8 8 24 8 8 user de?ed 8 8 user de?ed p f osc clock source frequency (excluding any prescaling) refer to 13.12 control timing (5.0 vdc) and 13.13 control timing (3.0 vdc) mhz 1. limited by requirement for c ext to be less than 2.0 f. 2. the desired type of capacitor for the ramp capacitor is any of the ?oly film types which have both low leakage and low dielec- tric absorption (somtimes referred to as memory behavior). low-cost monolithic ceramics are good for bypass use, but have high dielectric absorption which makes them less desirable for an integration or storage application. tantalum or aluminum electrolytics have high dielectric absorption and too much leakage, as well. for integration or storage capacitors use capacitors which have a dielectric absorption of less than 0.01%.
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 123 non-disclosure agreement required table 8-5. sample conversion timing (v dd = 5.0 vdc) bits counts v x (vdc) a/d method clock source f osc (mhz) t chg (ms) c ext ( f) 4 16 3.5 software loop (12 bus cycles) (24 f osc cycles) mode 0 or 1 (manual) low-power oscillator 0.1 3.840 0.110 external pin oscillator 1.0 0.384 0.011 2.0 0.192 0.006 4.0 0.096 0.003 4 16 3.5 programmable timer (prescaler = 8) mode 2 or 3 (tof->icf or ocf->icf) low-power oscillator 0.1 1.280 0.037 external pin oscillator 1.0 0.128 0.004 2.0 0.064 0.002 4.0 0.032 0.001 6 64 3.5 software loop (12 bus cycles) (24 f osc cycles) mode 0 or 1 (manual) low-power oscillator 0.1 15.36 0.439 external pin oscillator 1.0 1.536 0.044 2.0 0.768 0.022 4.0 0.384 0.011 6 64 3.5 programmable timer (prescaler = 8) mode 2 or 3 (tof->icf or ocf->icf) low-power oscillator 0.1 5.120 0.585 external pin oscillator 1.0 0.512 0.059 2.0 0.256 0.029 4.0 0.128 0.015 8 256 3.5 software loop (12 bus cycles) (24 f osc cycles) mode 0 or 1 (manual) low-power oscillator 0.1 61.44 1.755 external pin oscillator 1.0 6.144 0.176 2.0 3.072 0.088 4.0 1.536 0.044 8 256 3.5 programmable timer (prescaler = 8) mode 2 or 3 (tof->icf or ocf->icf) low-power oscillator 0.1 20.48 0.585 external pin oscillator 1.0 2.048 0.059 2.0 1.024 0.029 4.0 0.512 0.015 10 1024 3.5 programmable timer (prescaler = 8) mode 2 or 3 (tof->icf or ocf->icf) low-power oscillator 0.1 (note 1) (note 1) external pin oscillator 1.0 8.192 0.234 2.0 4.096 0.117 4.0 2.048 0.059 12 4096 3.5 programmable timer (prescaler = 8) mode 2 or 3 (tof->icf or ocf->icf) low-power oscillator 0.1 (note 1) (note 1) external pin oscillator 1.0 32.768 0.936 2.0 16.384 0.468 4.0 8.192 0.234 1. not usable because the value of c ext would be greater than 2.0 f
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 124 analog subsystem freescale semiconductor figure 8-8. a/d conversion ?full manual control (mode 0) t dis (min) t chg x i chg c ext t chg t dis v x = t max v max chg comp2 0 tof ocf icf (min) v cap t dis v x 1 2 3 4 1 5 point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 0 by clearing the chg, atd2, and atd1 control bits in the acr software write software 1v cap falls to v ss . wait out minimum t dis time v max , i dis , c ext 2 stop discharge and begin charge by setting chg control bit in acr. software write software 3 v cap rises to v x and comparator 2 output trips, setting cpf2 and cmp2. wait out t chg time v x , i chg , c ext 4v cap reaches v max . none v max , i chg , c ext 5 begin next discharge by clearing the chg control bit in the acr. reset cpf2 by writing a 1 to cpfr2. software write software
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 125 non-disclosure agreement required figure 8-9. a/d conversion ?manual/auto discharge control (mode 1) t dis (min) t chg x i chg c ext t chg t dis v x = v max chg comp2 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 2 point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 1 by clearing chg and atd2 and setting atd1 in the acr software write software 1v cap falls to v ss . wait out minimum t dis time v max , i dis , c ext 2 stop discharge and begin charge by setting chg control bit in acr. software write software 3 v cap rises to v x and comparator 2 output trips, setting cpf2 and cmp2, which clears chg control bit in the acr. reset cpf2 by writing a 1 to cpfr2. wait out t chg time cpf2 clears chg control bit v x , i chg , c ext
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 126 analog subsystem freescale semiconductor figure 8-10. a/d conversion ?tof/icf control (mode 2) t dis (min) t chg x i chg c ext t chg t dis v x = v max chg comp2 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 2 (tcap) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 2 by clearing chg and atd1 and setting atd2 in the acr. also set icen bit in acr and iedg bit in tcr. software write software 1v cap falls to v ss . wait out minimum t dis time. v max , i dis , c ext 2 stop discharge and begin charge when the next tof sets the chg control bit in acr. timer tof sets the chg control bit in the acr. free-running timer counter over?w, f osc 3 v cap rises to v x and comparator 2 output trips, setting cpf2 and cmp2, which causes an icf from the timer and clears the chg control bit in acr. must clear cpf2 to trap next cpf2 ?g. wait out t chg time. timer icf clears the chg control bit in the acr. v x , i chg , c ext
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 127 non-disclosure agreement required figure 8-11. a/d conversion ?ocf/icf control (mode 3) t dis (min) t chg x i chg c ext t chg t dis v x = v max chg comp2 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 2 (tcap) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 3 by clearing chg and setting atd2 and atd1 in the acr. also set icen bit in acr and iedg bit in tcr. software write software 1 v cap falls to v ss . set timer output compare registers (ocrh and ocrl) to desired charge start time. wait out minimum t dis time. software write to ocrh, ocrl v max , i dis , c ext , software 2 stop discharge and begin charge when the next ocf sets the chg control bit in acr. timer ocf sets the chg control bit in the acr. free-running timer output compare, f osc 3 v cap rises to v x and comparator 2 output trips, setting cpf2 and cmp2, which causes an icf from the timer and clears the chg control bit in acr. must clear cpf2 to trap next cpf2 ?g. load next ocf. wait out t chg time. timer icf clears the chg control bit in the acr. v x , i chg , c ext
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 128 analog subsystem freescale semiconductor 8.7 voltage measurement methods the methods for obtaining a voltage measurement can use software techniques to express these voltages as absolute or ratiometric readings. in most applications, the external capacitor, the clock source, the reference voltage and the charging current may vary between devices and with changes in supply voltage or ambient temperature. all of these variations must be considered when determining the desired resolution of the measurement. the maximum and minimum extremes for the full scale count will be: n fsmin = c extmin x v fsmin x f oscmin / (p x i chgmax ) n fsmax = c extmax x v fsmax x f oscmax / (p x i chgmin ) the minimum count should be the desired resolution; and the counting mechanism must be capable of counting to the maximum. the final scaling of the count will be by a math routine which calculates: v x = v ref x (n x ?n off ) / (n ref ?n off ) where: v ref = known reference voltage v x = unknown voltage between v ss and v ref n x = conversion count for unknown voltage n ref = conversion count for known reference voltage (v ref ) n off = conversion count for minimum reference voltage (v ss ) when v ref is a stable voltage source, such as a zener or other reference source, then the unknown voltage will be determined as an absolute reading. if v ref is the supply source to the device (v dd ), then the unknown voltage will be determined as a ratio of v dd or a ratiometric reading. if the unknown voltage applied to the comparator is greater than its common-mode range (v dd ?.5 volts), then the external capacitor will try to charge to the same level. this will cause both comparator inputs to be above the common-mode range and the output of the comparator will be indeterminate. in this case, the comparator output flags may also
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 129 non-disclosure agreement required be set even if the actual voltage on the positive input (+) is less than the voltage on the negative input (?. all a/d conversion methods should have a maximum time check to determine if this case is occurring. once the maximum timeout detection has been made, the state of the comparator outputs can be tested to determine the situation. however, such tests should be carefully designed when using modes 1, 2, or 3, as these modes cause the immediate automatic discharge of the external ramping capacitor before any software check can be made of the output state of comparator 2. note: all a/d conversion methods should include a test for a maximum elapsed time to detect error cases where the inputs may be outside of the design specification. 8.7.1 absolute voltage readings the absolute value of a voltage measurement can be calculated in software by first taking a reference reading from a fixed source and then comparing subsequent unknown voltages to that reading as a percentage of the reference voltage multiplied times the known reference value. the accuracy of absolute readings will depend on the error sources taken into account using the features of the analog subsystem and appropriate software as described in table 8-6 . as can be seen from this table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted comparator inputs, and averaging of multiple samples. 8.7.1.1 internal absolute reference if a stable source of v dd is provided, the reference measurement point can be internally selected. in this case, the reference reading can be taken by setting the v ref bit and clearing the mux1:mux4 bits in the amux register. this connects the channel selection bus to the v dd pin. to stay within the v max range, the dhold bit should be used to select the 1/2 divided input.
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 130 analog subsystem freescale semiconductor 8.7.1.2 external absolute reference if a stable external source is provided, the reference measurement point can be any one of the channel selected pins from pb1 through pb4. in this case, the reference reading can be taken by setting the mux bit in the amux which connects channel selection bus to the pin connected to the external reference source. if the external reference is greater than v dd ?.5 volts, then the dhold bit should be used to select the 1/2 divided input. table 8-6. absolute voltage reading errors error source accuracy improvements possible in hardware in software change in reference voltage provide closer tolerance reference calibration and storage of reference source over temperature and supply voltage change in magnitude of ramp current source not adjustable compare unknown with recent measurement from reference non-linearity of ramp current source vs. voltage not adjustable calibration and storage of voltages at 1/4, 1/2, 3/4, and fs change in magnitude of ramp capacitor provide closer tolerance ramp capacitor compare unknown with recent measurement from reference frequency shift in internal low-power oscillator use external oscillator with crystal compare unknown with recent measurement from reference frequency shift in external oscillator provide closer tolerance crystal compare unknown with recent measurement from reference sampling capacitor leakage use faster conversion times compare unknown with recent measurement from reference internal voltage divider ratio not adjustable compare unknown with recent measurement from reference or avoid use of divided input input offset voltage of comparator 2 not adjustable sum two readings on reference or unknown using inv and inv control bit and divide by 2 (average of both) noise internal to mcu close decoupling at v dd and v ss pins and reduce supply source impedance average multiple readings on both the reference and the unknown voltage noise external to mcu close decoupling of power supply, low source impedances, good board layout, use of multi-layer board average multiple readings on both the reference and the unknown voltage
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 131 non-disclosure agreement required 8.7.2 ratiometric voltage readings the ratiometric value of a voltage measurement can be calculated in software by first taking a reference reading from a reference source and then comparing subsequent unknown voltages to that reading as a percentage of the reference value. the accuracy of ratiometric readings will depend on the variety of sources, but will generally be better than for absolute readings. many of these error sources can be taken into account using the features of the analog subsystem and appropriate software as described in table 8-7 . as with absolute measurements, most of the errors can be reduced by frequent comparisons to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples. 8.7.2.1 internal ratiometric reference if readings are to be ratiometric to v dd , the reference measurement point can be internally selected. in this case, the reference reading can be taken by setting the vref bit and clearing the mux1:mux4 bits in the amux register, which connects the channel selection bus to the v dd pin. to stay within the v max range, the dhold bit should be used to select the 1/2 divided input. 8.7.2.2 external ratiometric reference if readings are to be ratiometric to some external source, the reference measurement point can be connected to any one of the channel selected pins from pb1 through pb4. in this case, the reference reading can be taken by setting the mux bit in the amux, which connects channel selection bus to the pin connected to the external reference source. if the external reference is greater than v dd ?.5 volts, then the dhold bit should be used to select the 1/2 divided input.
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 132 analog subsystem freescale semiconductor table 8-7. ratiometric voltage reading errors error source accuracy improvements possible in hardware in software change in reference voltage not required for ratiometric compare unknown with recent measurement from reference change in magnitude of ramp current source not adjustable compare unknown with recent measurement from reference non-linearity of ramp current source vs. voltage not adjustable calibration and storage of voltages at 1/4, 1/2, 3/4, and fs change in magnitude of ramp capacitor not required for ratiometric compare unknown with recent measurement from reference frequency shift in internal low-power oscillator not required for ratiometric compare unknown with recent measurement from reference frequency shift in external oscillator not required for ratiometric compare unknown with recent measurement from reference sampling capacitor leakage use faster conversion times compare unknown with recent measurement from reference internal voltage divider ratio not adjustable compare unknown with recent measurement from reference input offset voltage of comparator 2 not adjustable sum two readings on reference or unknown using inv and inv control bit and divide by 2 (average of both) noise internal to mcu close decoupling at v dd and v ss pins and reduce supply source impedance average multiple readings on both the reference and the unknown voltage noise external to mcu close decoupling of power supply, low source impedances, good board layout, use of multi-layer board average multiple readings on both the reference and the unknown voltage
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 133 non-disclosure agreement required 8.8 voltage comparator features the two internal comparators can be used as simple voltage comparators if set up as described in table 8-8 . both comparators can be active in the wait mode and can directly restart the part by means of the analog interrupt. both comparators can also be active in stop mode, but cannot directly restart the part. however, the comparators can directly drive a pa4 or pa5 pin, which can then be connected externally to activate either a port interrupt on the pa0:pa3 pins or the irq pin. voltage comparator 1 voltage comparator 1 is always connected to two of the port b i/o pins. these pins should be configured as inputs and have their software programmable pulldowns disabled. also, the negative input of voltage comparator 1 is connected to the pb3/an3/tcap and shared with the input capture function of the 16-bit programmable timer. therefore, the timer input capture interrupt should be disabled so that changes in the voltage on the pb3/an3/tcap pin do not cause unwanted input capture interrupts. the output of comparator 1 can be connected to the port logic driving the pb4/an4/tcmp/cmp1 pin such that the output of the comparator is ored with the pb4 data bit and the olvl bit from the 16-bit timer. this capability requires that the proper mask option and the coe1 bit set in the asr at location $001e. voltage comparator 2 voltage comparator 2 can be used as a simple comparator if its charge current source and discharge device are disabled by clearing the isen bit in the acr. if the isen bit is set, the internal ramp discharge device connected to pb0/an0 may become active and try table 8-8. voltage comparator setup conditions comparator current source enable discharge device disable port b pin as inputs port b pin pulldowns disabled prog. timer input capture source 1 not affected not affected ddrb2 = 0 ddrb3 = 0 pdib2 = 1 pdib3 = 1 not affected 2 isen = 0 isen = 0 ddrb0 = 0 ddrb1 = 0 pdib0 = 1 pdib1 = 1 icen = 0 iedg = 1
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 134 analog subsystem freescale semiconductor to pull down any voltage source that may be connected to that pin. also, since voltage comparator 2 is always connected to two of the port b i/o pins, these pins should be configured as inputs and have their software programmable pulldowns disabled. 8.9 current source features the internal current source connected to the pb0/an0 pin supplies about 100 a of current when the discharge device is disabled and the current source is active. therefore, this current source can be used in an application if the isen enable bit is set to power up the current source and by setting the a/d conversion method to manual mode 0 (atd1 and atd2 cleared) and the charge current is enabled (chg set). 8.10 internal temperature sensing diode features an internal diode is forward biased to v ss and will have its voltage change approximately 2 mv for each degree centigrade rise in the temperature of the device. this temperature-sensing diode is powered up from a current source only during the time that the diode is selected. when on, this current source adds about 30 a to the i dd current. the temperature-sensing diode can be selected by setting both the hold and dhold bits in the amux register (see 8.3 analog multiplex register ). 8.11 sample and hold when using the internal sample capacitor to capture a voltage for later conversion, the hold or dhold bit must be cleared first before changing any channel selection. if both the hold (or dhold) bit and the channel selection are changed on the same write cycle, the sample may be corrupted during the switching transitions.
analog subsystem mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor analog subsystem 135 non-disclosure agreement required note: the sample capacitor can be affected by excessive noise created with respect to the device? v ss pin such that it may appear to leak down or charge up depending on the voltage level stored on the sample capacitor. it is recommended to avoid switching large currents through the port pins while a voltage is to remain stored on the sample capacitor. the additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown voltages near v ss to be sampled and then shifted up past the comparator offset and the device offset caused by a single v ss return pin. this offset also provides a means to measure the internal v ss level, regardless of the comparator offset, to determine n off as described in 8.7 voltage measurement methods . in either case, the proper mask option must be selected and the voff bit must be set in the asr. it is not necessary to switch the voff bit during conversions, since the offset is controlled by the hold and dhold bits when the voff is active. refer to 8.3 analog multiplex register for more details on the design and decoding of the sample and hold circuit. 8.12 port b interaction with analog inputs the analog subsystem is connected directly to the port b i/o pins without any intervening gates. it is, therefore, possible to measure the voltages on port b pins set as inputs or to have the analog voltage measurements corrupted by port b pins set as outputs. 8.13 port b pins as inputs all the port b pins will power up as inputs or return to inputs after a reset of the device, since the bits in the port b data direction register will be reset. if any port b pins are to be used for analog voltage measurements, they should be left as inputs. in this case, not only can the voltage on the pin be measured, but the logic state of the port b pins can be read from location $0002.
non-disclosure agreement required analog subsystem general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 136 analog subsystem freescale semiconductor 8.14 port b pulldowns all the port b pins have internal software programmable pulldown devices available dependent on the software pulldown inhibit mask option. if the pulldowns are enabled, they will create an approximate 100- a load to any analog source connected to the pin. in some cases, the analog source may be able to supply this current without causing any error due to the analog source output impedance. since this may not always be true, it is therefore best to disable port b pulldowns on those pins used for analog input sources. 8.15 noise sensitivity in addition to the normal effects of electrical noise on the analog input signal, there can also be other noise-related effects caused by the digital-to-analog interface. since there is only one v ss return for both the digital and the analog subsystems on the device, currents in the digital section may affect the analog ground reference within the device. this can add voltage offsets to measured inputs or cause channel-to-channel crosstalk. to reduce the impact of these effects, there should be no switching of heavy i/o currents to or from the device while there is a critical analog conversion or voltage comparison in process. limiting switched i/o currents to 2 to 4 ma during these times is recommended. a noise reduction benefit can be gained with 0.1 f bypass capacitors from each analog input (pb4:pb1) to the v ss pin. also, try to keep all the digital power supply or load currents from passing through any conductors which are the return paths for an analog signal.
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor simple serial interface 137 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 9. simple serial interface 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 9.3 siop signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 9.3.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.3.3 serial data output (sdo) . . . . . . . . . . . . . . . . . . . . . . . . .140 9.4 siop registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.1 siop control register . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.2 siop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.4.3 siop data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 9.2 introduction the simple synchronous serial i/o port (siop) subsystem is designed to provide efficient serial communications with peripheral devices or other mcus. siop is implemented as a 3-wire master/slave system with serial clock (sck), serial data input (sdi), and serial data output (sdo). a block diagram of the siop is shown in figure 9-1 . the siop subsystem shares its input/output pins with port b. when the siop is enabled (spe bit set in the scr), the port b data direction and data registers are bypassed by the siop. the port b data direction and data registers will remain accessible and can be altered by the application software, but these actions will not affect the siop transmitted or received data.
non-disclosure agreement required simple serial interface general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 138 simple serial interface freescale semiconductor figure 9-1. siop block diagram portb logic siop interrupt pb7 sck pb6 sdi pb5 sdo sdr0 sdr1 sdr2 sdr3 sdr4 sdr5 sdr6 sdr7 siop internal hc05 bus spe siop control register (scr) spie data register (sdr) dcol siop status register (ssr) spif format control spir 8-bit shift lsbf latch s r register din dout clk clock control mstr cpha spr1 spr0 clock divider oscillator clock q lsb or msb first portb logic portb logic and select d0 d1 d2 d3 d4 d5 d6 d7 internal hc05 bus comp error 2 $000a $000b $000c
simple serial interface mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor simple serial interface 139 non-disclosure agreement required 9.3 siop signal format the siop subsystem can be software configured for master or slave operation. no external mode selection inputs are available (for instance, no slave select pin). 9.3.1 serial clock (sck) the state of the sck output remains a fixed logic level during idle periods between data transfers. the edges of sck indicate the beginning of each output data transfer and latch any incoming data received. the first bit of transmitted data is output from the sdo pin on the first falling edge of sck. the first bit of received data is accepted at the sdi pin on the first rising edge of sck after the first falling edge. the transfer is terminated upon the eighth rising edge of sck. the idle state of the sck is determined by the state of the cpha bit in the scr. when the cpha is clear, sck will remain idle at a logical one as shown in figure 9-2 . when the cpha is set, sck will remain idle at a logical zero as shown in figure 9-3 . in both cases, the sdo changes data on the falling edge of the sck, and the sdi latches data in on the rising edge of sck. the master and slave modes of operation differ only in the means of sourcing the sck. in master mode, sck is driven from an internal source within the mcu. in slave mode, sck is driven from a source external to the mcu. the sck frequency is based on one of four divisions of the oscillator clock that is selected by the spr0 and spr1 bits in the scr. figure 9-2. siop timing diagram (cpha = 0) sck sdo sdi 100 ns 100 ns bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (cpha = 0) (idle = 1)
non-disclosure agreement required simple serial interface general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 140 simple serial interface freescale semiconductor figure 9-3. siop timing diagram (cpha = 1) 9.3.2 serial data input (sdi) the sdi pin becomes an input as soon as the siop subsystem is enabled. new data is presented to the sdi pin on the falling edge of sck. valid data must be present at least 100 nanoseconds before the rising edge of sck and remain valid for 100 nanoseconds after the rising edge of sck. see figure 9-3 . 9.3.3 serial data output (sdo) the sdo pin becomes an output as soon as the siop subsystem is enabled. the state of the pb5/sdo pin reflects the value of the first bit received on the previous transmission. prior to enabling the siop, the pb5/sdo can be initialized to determine the beginning state. while siop is enabled, the port b logic cannot be used as a standard output since that pin is connected to the last stage of the siop serial shift register. a control bit (lsbf) is included in the scr to allow the data to be transmitted in either the msb first format or the lsb first format. the first data bit will be shifted out to the sdo pin on the first falling edge of the sck. the remaining data bits will be shifted out to the sdi pin on subsequent falling edges of sck. the sdo pin will present valid data at least 100 nanoseconds before the rising edge of the sck and remain valid for 100 nanoseconds after the rising edge of sck. see figure 9-3 . sck sdo sdi 100 ns 100 ns bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (cpha = 1) (idle = 0)
simple serial interface mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor simple serial interface 141 non-disclosure agreement required 9.4 siop registers the siop is programmed and controlled by the siop control register (scr) located at address $000a, the siop status register (ssr) located at address $000b, and the siop data register (sdr) located at address $000c. 9.4.1 siop control register the siop control register (scr) is located at address $000a and contains seven control bits and a write-only reset of the interrupt flag. figure 9-4 shows the position of each bit in the register and indicates the value of each bit after reset. spie ?serial peripheral interrupt enable the spie bit enables the siop to generate an interrupt whenever the spif flag bit in the ssr is set. clearing the spie bit will not affect the state of the spif flag bit and will not terminate a serial interrupt once the interrupt sequence has started. reset clears the spie bit. 1 = serial interrupt enabled 0 = serial interrupt disabled note: if the spie bit is cleared just after the serial interrupt sequence has started (for instance, the cpu status is being stacked), then the cpu will be unable to determine the source of the interrupt and will vector to the reset vector as a default. $000a bit 7 654321 bit 0 read: spie spe lsbf mstr 0 cpha spr1 spr0 write: spir reset: 00000000 figure 9-4. siop control register (scr)
non-disclosure agreement required simple serial interface general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 142 simple serial interface freescale semiconductor spe ?serial peripheral enable the spe bit switches the port b interface such that sdo/pb5 is the serial data output, sdi/pb6 is the serial data input, and sck/pb7 is a serial clock input in the slave mode or a serial clock output in the master mode. the port b ddr and data registers can be manipulated as usual, but these actions will not affect the transmitted or received data. the spe bit is readable and writable at any time, but clearing the spe bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert port b to a general-purpose i/o port. reset clears the spe bit. 1 = serial peripheral enabled (port b i/o disabled) 0 = serial peripheral disabled (port b i/o enabled) lsbf ?least significant bit first the lsbf bit controls the format of the transmitted and received data to be transferred lsb or msb first. reset clears this bit. 1 = lsb transferred first 0 = msb transferred first mstr ?master mode select the mstr bit configures the serial i/o port for master mode. a transfer is initiated by writing to the sdr. also, the sck pin becomes an output providing a synchronous data clock dependent upon the divider of the oscillator frequency selected by the spr0:spr1 bits. when the device is in master mode, the sdo and sdi pins do not change function. these pins behave exactly the same in both the master and slave modes. the mstr bit is readable and writable at any time regardless of the state of the spe bit. clearing the mstr bit will abort any transfers that may have been in progress. reset clears the mstr bit, placing the siop subsystem in slave mode. 1 = siop set up as master, sck is an output 0 = siop set up as slave, sck is an input
simple serial interface mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor simple serial interface 143 non-disclosure agreement required spir ?serial peripheral interrupt reset the spir bit is a write-only control to reset the spif flag bit in the ssr. reading the spir bit will return a logical zero. 1 = reset the spif flag bit 0 = no effect cpha ?clock phase the cpha bit controls the clock timing and phase in the siop. data is changed on the falling edge of sck and data is captured (read) on the rising edge of sck. this bit is cleared by reset. 1 = sck idle low 0 = sck idle high spr0:spr1 ?serial peripheral clock rate selects the spr0 and spr1 bits select one of four clock rates given in table 9-1 to be supplied on the pb7/sck pin when the device is configured with the siop as a master (mstr = 1). the fastest rate is when both spr0 and spr1 are set. both the spr0 and spr1 bits are cleared by reset, which places the siop clock selection at the slowest rate. table 9-1. siop clock rate selection spr1 spr0 siop clock rate (oscillator frequency divided by:) 00 64 01 32 10 16 11 8
non-disclosure agreement required simple serial interface general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 144 simple serial interface freescale semiconductor 9.4.2 siop status register the siop status register (ssr) is located at address $000b and contains two read-only bits. figure 9-5 shows the position of each bit in the register and indicates the value of each bit after reset. spif ?serial port interrupt flag the spif is a read-only status bit that is set on the last rising edge of sck and indicates that a data transfer has been completed. it has no effect on any future data transfers and can be ignored. the spif bit can be cleared by reading the ssr followed by a read or write of the sdr or by writing a logical one to the spir bit in the scr. if the spif is cleared before the last rising edge of sck it will be set again on the last rising edge of sck. reset clears the spif bit. 1 = serial transfer complete, serial interrupt if the spie bit in scr is set 0 = serial transfer in progress or serial interface idle dcol ?data collision the dcol is a read-only status bit which indicates that an illegal access of the sdr has occurred. the dcol bit will be set when reading or writing the sdr after the first falling edge of sck and before spif is set. reading or writing the sdr during this time will result in invalid data being transmitted or received. the dcol bit is cleared by reading the ssr (when the spif bit is set) followed by a read or write of the sdr. if the last part of the clearing sequence is done after another transfer has started, the dcol bit will be set again. reset clears the dcol bit. 1 = illegal access of the sdr occurred 0 = no illegal access of the sdr detected $000b bit 7 654321 bit 0 read: spif dcol 000000 write: reset: 00000000 = unimplemented figure 9-5. siop status register (ssr)
simple serial interface mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor simple serial interface 145 non-disclosure agreement required 9.4.3 siop data register the siop data register (sdr) is located at address $000c and serves as both the transmit and receive data register. writing to this register will initiate a message transmission if the node is in master mode. the siop subsystem is not double buffered and any write to this register will destroy the previous contents. the sdr can be read at any time. however, if a transfer is in progress, the results may be ambiguous. writing to the sdr while a transfer is in progress can cause invalid data to be transmitted and/or received. figure 9-6 shows the position of each bit in the register. this register is not affected by reset. $000c bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset figure 9-6. siop data register (sdr)
non-disclosure agreement required simple serial interface general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 146 simple serial interface freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor core timer 147 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 10. core timer 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.3 core timer status and control register . . . . . . . . . . . . . . . .149 10.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . .151 10.5 cop watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 10.2 introduction this section describes the operation of the core timer and the cop watchdog as shown by the block diagram in figure 10-1 .
non-disclosure agreement required core timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 148 core timer freescale semiconductor figure 10-1. core timer block diagram bits 0? of 15-stage internal data bus ripple counter cop register rti rate select 2 2 2 2 2 2 2 2 reset cop watchdog reset power-on reset internal clock 1024 ctof rtif ctofe rtie ctofr rtifr rt1 rt0 core timer request interrupt core timer status/control register copc 2 2 2 reset core timer counter register overflow reset 4 osc1 2 internal clock $0009 $0008 $1ff0
core timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor core timer 149 non-disclosure agreement required 10.3 core timer status and control register the read/write core timer status and control register (ctscr) contains the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in figure 10-2 . ctof ?core timer overflow flag this read-only flag becomes set when the first eight stages of the core timer counter roll over from $ff to $00. the ctof flag bit generates a timer overflow interrupt request if ctofe is also set. the ctof flag bit is cleared by writing a logic one to the ctofr bit. writing to ctof has no effect. reset clears ctof. 1 = overflow in core timer has occurred. 0 = no overflow of core timer since ctof last cleared rtif ?real-time interrupt flag this read-only flag becomes set when the selected rti output becomes active. rtif generates a real-time interrupt request if rtie is also set. the rtif enable bit is cleared by writing a logic one to the rtifr bit. writing to rtif has no effect. reset clears rtif. 1 = overflow in real-time counter has occurred. 0 = no overflow of real-time counter since rtif last cleared ctofe ?core timer overflow interrupt enable this read/write bit enables core timer overflow interrupts. reset clears ctofe. 1 = core timer overflow interrupts enabled 0 = core timer overflow interrupts disabled $0008 bit 7 654321 bit 0 read: ctof rtif ctofe rtie 00 rt1 rt0 write: ctofr rtifr reset: 00000011 = unimplemented figure 10-2. core timer status and control register (ctscr)
non-disclosure agreement required core timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 150 core timer freescale semiconductor rtie ?real-time interrupt enable this read/write bit enables real-time interrupts. reset clears rtie. 1 = real-time interrupts enabled 0 = real-time interrupts disabled ctofr ?core timer overflow flag reset writing a logic one to this write-only bit clears the ctof bit. ctofr always reads as a logic zero. reset does not affect ctofr. 1 = clear ctof flag bit 0 = no effect on ctof flag bit rtifr ?real-time interrupt flag reset writing a logic one to this write-only bit clears the rtif bit. rtifr always reads as a logic zero. reset does not affect rtifr. 1 = clear rtif flag bit 0 = no effect on rtif flag bit rt1 and rt0 ?real-time interrupt select bits 1 and 0 these read/write bits select one of four real-time interrupt rates, as shown in table 10-1 . because the selected rti output drives the cop watchdog, changing the real-time interrupt rate also changes the counting rate of the cop watchdog. reset sets rt1 and rt0, selecting the longest cop timeout period and longest real-time interrupt period. note: changing rt1 and rt0 when a cop timeout is imminent or uncertain may cause a real-time interrupt request to be missed or an additional real-time interrupt request to be generated. clear the cop timer just before changing rt1 and rt0.
core timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor core timer 151 non-disclosure agreement required 10.4 core timer counter register a 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. the value of the first eight stages is readable at any time from the read-only timer counter register as shown in figure 10-3 . power-on clears the entire counter chain and begins clocking the counter. after the startup delay (16 or 4064 internal bus cycles depending on a mask option), the power-on reset circuit is released, clearing the counter again and allowing the mcu to come out of reset. each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. a timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock cycles or every 1024 internal bus cycles. table 10-1. core timer interrupt rates and cop timeout selection timer overflow interrupt period tof = 1/(f osc 2 11 ) (microseconds) rt1 rt0 rti rate = f osc divided by: real-time interrupt period (rti) (milliseconds) cop timeout period cop = 7 to 8 rti periods (milliseconds) @ f osc (mhz) @ f osc (mhz) @ f osc (mhz) 4.2 mhz 2.0 mhz 1.0 mhz 4.2 mhz 2.0 mhz 1.0 mhz 4.2 mhz 2.0 mhz 1.0 mhz min max min max min max 488 1024 2048 00 2 15 7.80 16.4 32.8 54.6 62.4 115 131 229 262 01 2 16 15.6 32.8 65.5 109 125 229 262 459 524 10 2 17 31.2 65.5 131 218 250 459 524 918 1049 11 2 18 62.4 131 262 437 499 918 1049 1835 2097 $0009 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 = unimplemented figure 10-3. core timer counter register (ctcr)
non-disclosure agreement required core timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 152 core timer freescale semiconductor 10.5 cop watchdog four counter stages at the end of the core timer make up the computer operating properly (cop) watchdog which can be enabled by a mask option. the cop watchdog is a software error detection system that automatically times out and resets the mcu if the cop watchdog is not cleared periodically by a program sequence. writing a logic zero to copc bit in the cop register clears the cop watchdog and prevents a cop reset. copc ?cop clear this write-only bit resets the cop watchdog. the cop watchdog is active in the run, wait, and halt modes of operation if the cop is enabled by a mask option. the stop instruction disables the cop watchdog by clearing the counter and turning off its clock source. in applications that depend on the cop watchdog, the stop instruction can be disabled by the stop mask option. in applications that have wait cycles longer than the cop timeout period, the cop watchdog can be disabled by the stop mask option. table 10-2 summarizes recommended conditions for enabling and disabling the cop watchdog. note: if the voltage on the irq pin exceeds 1.5 v dd , the cop watchdog turns off and remains off until the irq pin voltage falls below 1.5 v dd . $1ff0 bit 7 654321 bit 0 read: write: copc reset: unaffected by reset = unimplemented figure 10-4. cop and security register (copr)
core timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor core timer 153 non-disclosure agreement required table 10-2. cop watchdog recommendations voltage on irq pin mask option to select halt 1 wait/halt time recommended cop watchdog condition less than 1.5 v dd 1 less than cop timeout period enabled 2 less than 1.5 v dd 1 greater than cop timeout period disabled less than 1.5 v dd 0x 3 disabled more than 1.5 v dd x x disabled notes: 1. the halt mask option converts stop instructions to halt instructions. 2. reset the cop watchdog immediately before executing the wait/halt instruction. 3. x = don? care
non-disclosure agreement required core timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 154 core timer freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 155 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 11. programmable timer 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 11.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 11.4 alternate counter registers . . . . . . . . . . . . . . . . . . . . . . . . .160 11.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 11.6 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . .164 11.7 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.8 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.9 timer operation during wait mode. . . . . . . . . . . . . . . . . . . . .169 11.10 timer operation during stop mode . . . . . . . . . . . . . . . . . . . .169 11.11 timer operation during halt mode . . . . . . . . . . . . . . . . . . . . .169
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 156 programmable timer freescale semiconductor 11.2 introduction the mc68hc05jj6/mc68hc05jp6 mcu contains a 16-bit programmable timer with an input capture function and an output compare function as shown by the block diagram in figure 11-1 . the basis of the capture/compare timer is a 16-bit free-running counter which increases in count with every four internal bus clock cycles. the counter is the timing reference for the input capture and output compare functions. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. the i/o registers for the input capture and output compare functions are pairs of 8-bit registers, because of the 16-bit timer architecture used. each register pair contains the high and low bytes of that function. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. because the counter is 16 bits long and preceded by a fixed divide-by- four prescaler, the counter rolls over every 262,144 internal clock cycles (every 524,288 oscillator clock cycles). timer resolution with a 4-mhz crystal oscillator is 2 microsecond/count. the interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (tcr) located at $0012, and the status of the interrupt flags can be read from the timer status register (tsr) located at $0013.
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 157 non-disclosure agreement required figure 11-1. programmable timer overall block diagram iedg olvl icie ocie toie tmrh ($0018) tmrl ($0019) 16-bit counter 4 internal (osc 2) timer control register timer request overflow (tof) reset clock interrupt acrh ($001a) acrl ($001b) 16-bit comparator ocrh ($0016) ocrl ($0017) pin i/o logic pb4 an4 tcmp pb3 an3 tcap edge select & detect icf ocf tof timer status register iedg icf ocf olvl $0012 $0013 internal data bus logic input select mux cpf2 flag icen control bit bit from analog subsystem icrh ($0014) icrl ($0015) d c q analog comp 1
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 158 programmable timer freescale semiconductor 11.3 timer registers the functional block diagram of the 16-bit, free-running timer counter and timer registers is shown in figure 11-2 . the timer registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 11-2. programmable timer block diagram the timer registers (tmrh and tmrl) shown in figure 11-3 are read- only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the timer registers has no effect. reset of the device presets the timer counter to $fffc. toie tmrh ($0018) tmr lsb 16-bit counter 4 internal (osc 2) timer control reg. timer request overflow (tof) reset clock interrupt tmrl ($0019) tof timer status reg. $0012 $0013 internal ($fffc) data read tmrh read tmrl read latch bus
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 159 non-disclosure agreement required the tmrl latch is a transparent read of the lsb until a read of the tmrh takes place. a read of the tmrh latches the lsb into the tmrl location until the tmrl is again read. the latched value remains fixed even if multiple reads of the tmrh take place before the next read of the tmrl. therefore, when reading the msb of the timer at tmrh, the lsb of the timer at tmrl must also be read to complete the read sequence. during power-on reset (por), the counter is initialized to $fffc and begins counting after the oscillator startup delay. because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). when the free-running counter rolls over from $ffff to $0000, the timer overflow flag bit (tof) is set in the tsr. when the tof is set, it can generate an interrupt if the timer overflow interrupt enable bit (toie) is also set in the tcr. the tof flag bit can only be reset by reading the tmrl after reading the tsr. other than clearing any possible tof flags, reading the tmrh and tmrl in any order or any number of times does not have any effect on the 16-bit free-running counter. $0018 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $0019 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111100 = unimplemented figure 11-3. programmable timer registers (tmrh and tmrl)
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 160 programmable timer freescale semiconductor note: to prevent interrupts from occurring between readings of the tmrh and tmrl, set the i bit in the condition code register (ccr) before reading tmrh and clear the i bit after reading tmrl. 11.4 alternate counter registers the functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in figure 11-4 . the alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the tof flag bit and timer interrupts. the alternate counter registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 11-4. alternate counter block diagram the alternate counter registers (acrh and acrl) shown in figure 11-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the alternate counter registers has no effect. reset of the device presets the timer counter to $fffc. acrh ($001a) tmr lsb 16-bit counter 4 internal (osc 2) reset clock acrl ($001b) internal ($fffc) data read acrh read acrl read latch bus
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 161 non-disclosure agreement required the acrl latch is a transparent read of the lsb until a read of the acrh takes place. a read of the acrh latches the lsb into the acrl location until the acrl is again read. the latched value remains fixed even if multiple reads of the acrh take place before the next read of the acrl. therefore, when reading the msb of the timer at acrh, the lsb of the timer at acrl must also be read to complete the read sequence. during power-on reset (por), the counter is initialized to $fffc and begins counting after the oscillator startup delay. because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). reading the acrh and acrl in any order or any number of times does not have any effect on the 16-bit free-running counter or the tof flag bit. note: to prevent interrupts from occurring between readings of the acrh and acrl, set the i bit in the condition code register (ccr) before reading acrh and clear the i bit after reading acrl. $001a bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $001b bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111100 = unimplemented figure 11-5. alternate counter registers (acrh and acrl)
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 162 programmable timer freescale semiconductor 11.5 input capture registers the input capture function is a means to record the time at which an event occurs. the source of the event can be the change on an external pin (pb3/an3/tcap) or the cpf2 flag bit of voltage comparator 2 in the analog subsystem. the icen bit in the analog subsystem control register (acr) at $001d selects which source is the input signal. when the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input capture registers as shown in figure 11-6 . note: both the icen bit in the acr and the iedg bit in the tcr must be set when using voltage comparator 2 to trigger the input capture function. latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. figure 11-6. timer input capture block diagram icie icrh ($0014) 16-bit counter 4 internal (osc 2) timer control reg. timer request input capture (icf) reset clock interrupt icrl ($0015) icf timer status reg. $0012 $0013 internal ($fffc) data read icrh read icrl latch bus iedg edge select & detect logic iedg pb3 an3 tcap input select mux cpf2 flag icen control bit bit from analog subsystem internal data bus
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 163 non-disclosure agreement required the input capture registers are made up of two 8-bit read-only registers (icrh and icrl) as shown in figure 11-7 . the input capture edge detector contains a schmitt trigger to improve noise immunity. the edge that triggers the counter transfer is defined by the input edge bit (iedg) in the tcr. reset does not affect the contents of the input capture registers. the result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). reading the icrh inhibits future captures until the icrl is also read. reading the icrl after reading the timer status register (tsr) clears the icf flag bit. there is no conflict between reading the icrl and transfers from the free-running timer counters. the input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. note: to prevent interrupts from occurring between readings of the icrh and icrl, set the i bit in the condition code register (ccr) before reading icrh and clear the i bit after reading icrl. $0014 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0015 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset = unimplemented figure 11-7. input capture registers (icrh and icrl)
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 164 programmable timer freescale semiconductor 11.6 output compare registers the output compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in figure 11-8 . software writes the selected value into the output compare registers. on every fourth internal clock cycle (every eight oscillator clock cycles), the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. when a match occurs, the timer transfers the output level (olvl) from the timer control register (tcr) to the pb4/an4/tcmp pin. software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the pb4/an4/tcmp pin. figure 11-8. timer output compare block diagram ocie ocrh ($0016) 16-bit counter 4 internal (osc 2) timer control reg. timer request output compare reset clock interrupt ocrl ($0017) ocf timer status reg. $0012 $0013 internal ($fffc) data r/w ocrh r/w ocrl bus olvl pb4 an4 tcmp edge select detect logic olvl 16-bit comparator (ocf)
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 165 non-disclosure agreement required the planned action on the pb4/an4/tcmp pin depends on the value stored in the olvl bit in the tcr, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in figure 11-9 . these registers are read/write bits and are unaffected by reset. writing to the ocrh before writing to the ocrl inhibits timer compares until the ocrl is written. reading or writing to the ocrl after reading the tcr will clear the output compare flag bit (ocf). the output compare olvl state will be clocked to its output latch regardless of the state of the ocf. to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. disable interrupts by setting the i bit in the condition code register. 2. write to the ocrh. compares are now inhibited until ocrl is written. 3. read the tsr to arm the ocf for clearing. 4. enable the output compare registers by writing to the ocrl. this also clears the ocf flag bit in the tsr. 5. enable interrupts by clearing the i bit in the condition code register. $0016 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0017 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset figure 11-9. output compare registers (ocrh and ocrl)
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 166 programmable timer freescale semiconductor a software example of this procedure is shown in table 11-1 . 11.7 timer control register the timer control register shown in figure 11-10 , performs these functions: enables input capture interrupts enables output compare interrupts enables timer overflow interrupts controls the active edge polarity of the tcap signal controls the active level of the tcmp output reset clears all the bits in the tcr with the exception of the iedg bit which is unaffected. table 11-1. output compare initialization example 9b ... ... b7 b6 bf ... ... 9a 16 13 17 sei ... ... sta lda stx ... ... cli ocrh tsr ocrl disable interrupts ..... ..... inhibit output compare arm ocf flag for clearing ready for next compare, ocf cleared ..... ..... enable interrupts $0012 bit 7 654321 bit 0 read: icie ocie toie 000 iedg olvl write: reset: 000000u0 = unimplemented u = unaffected figure 11-10. timer control register (tcr)
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 167 non-disclosure agreement required icie ?input capture interrupt enable this read/write bit enables interrupts caused by an active signal on the tcap pin or from cpf2 flag bit of the analog subsystem voltage comparator 2. reset clears the icie bit. 1 = input capture interrupts enabled 0 = input capture interrupts disabled ocie ?output compare interrupt enable this read/write bit enables interrupts caused by an active match of the output compare function. reset clears the ocie bit. 1 = output compare interrupts enabled 0 = output compare interrupts disabled toie ?timer overflow interrupt enable this read/write bit enables interrupts caused by a timer overflow. reset clears the toie bit. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled iedg ?input capture edge select the state of this read/write bit determines whether a positive or negative transition triggers a transfer of the contents of the timer register to the input capture register. this transfer can occur due to transitions on the tcap pin or the cpf2 flag bit of voltage comparator 2. resets have no effect on the iedg bit. 1 = positive edge (low-to-high transition) triggers input capture 0 = negative edge (high-to-low transition) triggers input capture note: the iedg bit must be set when either mode 2 or mode 3 of the analog subsystem is being used for a/d conversions. otherwise, the input capture will not occur on the rising edge of the comparator 2 flag. olvl ?output compare output level select the state of this read/write bit determines whether a logic one or a logic zero is transferred to the tcmp pin when a successful output compare occurs. resets clear the olvl bit. 1 = signal to tcmp pin goes high on output compare 0 = signal to tcmp pin goes low on output compare
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 168 programmable timer freescale semiconductor 11.8 timer status register the timer status register (tsr) shown in figure 11-11 contains flags for these events: an active signal on the tcap pin or the cpf2 flag bit of voltage comparator 2 in the analog subsystem, transferring the contents of the timer registers to the input capture registers a match between the 16-bit counter and the output compare registers, transferring the olvl bit to the pb4/an4/tcmp pin if that pin is set as an output an overflow of the timer registers from $ffff to $0000 writing to any of the bits in the tsr has no effect. reset does not change the state of any of the flag bits in the tsr. icf ?input capture flag the icf bit is set automatically when an edge of the selected polarity occurs on the tcap pin. clear the icf bit by reading the timer status register with the icf set and then reading the low byte (icrl, $0015) of the input capture registers. resets have no effect on icf. ocf ?output compare flag the ocf bit is set automatically when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with the ocf set and then accessing the low byte (ocrl, $0017) of the output compare registers. resets have no effect on ocf. $0013 bit 7 654321 bit 0 read: icf ocf tof 00000 write: reset: u u u 00000 = unimplemented u = unaffected figure 11-11. timer status register (tsr)
programmable timer mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor programmable timer 169 non-disclosure agreement required tof ?timer overflow flag the tof bit is set automatically when the 16-bit timer counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with the tof set and then accessing the low byte (tmrl, $0019) of the timer registers. resets have no effect on tof. 11.9 timer operation during wait mode during wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the mcu out of wait mode. 11.10 timer operation during stop mode when the mcu enters stop mode, the free-running counter stops counting (the internal processor clock is stopped). it remains at that particular count value until stop mode is exited by applying a low signal to the irq pin, at which time the counter resumes from its stopped value as if nothing had happened. if stop mode is exited via an external reset (logic low applied to the reset pin), the counter is forced to $fffc. if a valid input capture edge occurs during stop mode, the input capture detect circuitry will be armed. this action does not set any flags or wake up the mcu, but when the mcu does wake up there will be an active input capture flag (and data) from the first valid edge. if the stop mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode. 11.11 timer operation during halt mode when the mcu enters halt mode, the functions and states of the 16-bit programmable timer are the same as for wait mode described above.
non-disclosure agreement required programmable timer general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 170 programmable timer freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 171 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 12. instruction set 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .176 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .177 12.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .178 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .180 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 172 instruction set freescale semiconductor 12.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 12.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 173 non-disclosure agreement required 12.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 12.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 12.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 12.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction.
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 174 instruction set freescale semiconductor 12.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 12.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12.3.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the freescale assembler determines the shortest form of indexed addressing.
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 175 non-disclosure agreement required 12.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two? complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 12.4 instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 176 instruction set freescale semiconductor 12.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 12-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 177 non-disclosure agreement required 12.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 12-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value.
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 178 instruction set freescale semiconductor 12.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register.
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 179 non-disclosure agreement required table 12-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 180 instruction set freescale semiconductor 12.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 12-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 181 non-disclosure agreement required 12.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 12-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 182 instruction set freescale semiconductor 12.5 instruction set summary table 12-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? ??? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? ??? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ??? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ??? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 183 non-disclosure agreement required bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ?1; push (pch) sp (sp) ?1 pc (pc) + rel rel ad rr 6 clc clear carry bit c 0 0 inh 98 2 cli clear interrupt mask i 0 0 inh 9a 2 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 184 instruction set freescale semiconductor clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) ??? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ( m) = $ff ?(m) a ( a) = $ff ?(a) x ( x) = $ff ?(x) m ( m) = $ff ?(m) m ( m) = $ff ?(m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) ??? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ?1 a (a) ?1 x (x) ?1 m (m) ?1 m (m) ?1 ?? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 185 non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ?1 push (pch); sp (sp) ?1 pc effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ??? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 ?? dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ?m) = $00 ?(m) a ?a) = $00 ?(a) x ?x) = $00 ?(x) m ?m) = $00 ?(m) m ?m) = $00 ?(m) ??? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ??? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7
non-disclosure agreement required instruction set general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 186 instruction set freescale semiconductor ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ??? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ?(m) ?(c) ??? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 1 inh 99 2 sei set interrupt mask i 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ?(m) ??? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ?1; push (pch) sp (sp) ?1; push (x) sp (sp) ?1; push (a) sp (sp) ?1; push (ccr) sp (sp) ?1; i 1 pch interrupt vector high byte pcl interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x (a) inh 97 2 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c
instruction set mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor instruction set 187 non-disclosure agreement required 12.6 opcode map see table 12-7 . tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 ?? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?g pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?g z zero ?g hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?g ? set or cleared n any bit not affected table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 188 instruction set freescale semiconductor instruction set table 12-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 189 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 13. electrical specifications 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .191 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 13.6 supply current characteristics (v dd = 4.5 to 5.5 vdc). . . . . .192 13.7 supply current characteristics (v dd = 2.7 to 3.3 vdc). . . . . .193 13.8 dc electrical characteristics (5.0 vdc). . . . . . . . . . . . . . . . . .194 13.9 dc electrical characteristics (3.0 vdc). . . . . . . . . . . . . . . . . .195 13.10 analog subsystem characteristics (5.0 vdc) . . . . . . . . . . . . .198 13.11 analog subsystem characteristics (3.0 vdc) . . . . . . . . . . . . .199 13.12 control timing (5.0 vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.13 control timing (3.0 vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.14 siop timing (v dd = 5.0 vdc) . . . . . . . . . . . . . . . . . . . . . . . . .202 13.15 siop timing (v dd = 3.0 vdc) . . . . . . . . . . . . . . . . . . . . . . . . .203 13.16 reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 190 electrical specifications freescale semiconductor 13.2 introduction this section contains the electrical and timing specifications. 13.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 13.8 dc electrical characteristics (5.0 vdc) and 13.9 dc electrical characteristics (3.0 vdc) for guaranteed operating conditions. rating symbol value unit supply voltage v dd ?.3 to +7.0 v self-check mode ( irq pin only) v in v ss ?.3 to + 12 v current drain per pin excluding v dd and v ss i25ma operating junction temperature t j +150 c storage temperature range t stg ?5 to +150 c
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 191 non-disclosure agreement required 13.4 operating temperature range 13.5 thermal characteristics characteristic symbol value unit operating temperature range extended t a t l to t h ?0 to +85 c characteristic symbol value unit thermal resistance plastic soic ja 60 c/w
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 192 electrical specifications freescale semiconductor 13.6 supply current characteristics (v dd = 4.5 to 5.5 vdc) characteristic symbol min typ max unit run (analog and lvr disabled) internal low-power oscillator at 100 khz internal low-power oscillator at 500 khz external oscillator running at 4.2 mhz i dd 150 375 3.00 568 1100 5.20 a a ma wait (analog and lvr disabled) internal low-power oscillator at 100 khz internal low-power oscillator at 500 khz external oscillator running at 4.2 mhz i dd 45 75 1.00 85 375 2.20 a a ma stop (analog and lvr disabled) 25 c ?0 c to 85 c i dd 2 4 10 20 a a incremental i dd for enabled modules lv r analog subsystem i dd 5 380 15 475 a a notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 v, t l t a t h , unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 pin or internal oscillator, all inputs 0.2 vdc from either supply rail (v dd or v ss ); no dc loads, less than 50 pf on all outputs, c l =20pfon osc2. 5. wait i dd is affected linearly by the osc2 capacitance. 6. stop i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd ?.2 vdc, osc1 = v dd .
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 193 non-disclosure agreement required 13.7 supply current characteristics (v dd = 2.7 to 3.3 vdc) characteristic symbol min typ max unit run (analog and lvr disabled) internal low-power oscillator at 100 khz internal low-power oscillator at 500 khz external oscillator running at 2.1 mhz i dd 70 320 1.25 320 800 2.60 a a ma wait (analog and lvr disabled) internal low-power oscillator at 100 khz internal low-power oscillator at 500 khz external oscillator running at 2.1 mhz i dd 20 40 0.50 65 250 1.10 a a ma stop (analog and lvr disabled) 25 c ?0 c to 85 c i dd 1 2 5 10 a a incremental i dd for enabled modules lv r analog subsystem i dd 5 380 15 475 a a notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 v, t l t a t h , unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 pin or internal oscillator, all inputs 0.2 vdc from either supply rail (v dd or v ss ); no dc loads, less than 50 pf on all outputs, c l =20pfon osc2. 5. wait i dd is affected linearly by the osc2 capacitance. 6. stop i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd ?.2 vdc, osc1 = v dd .
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 194 electrical specifications freescale semiconductor 13.8 dc electrical characteristics (5.0 vdc) characteristic symbol min typ max unit output voltage i load = 10.0 a i load = ?0.0 a v ol v oh v dd ?.1 0.1 v output high voltage (i load = ?.8 ma) pb0:pb7 (i load = ?.0 ma) pa0:pa5, pb4, pc0:pc7 v oh v dd ?.8 v dd ?.8 v output low voltage (i load = 1.6 ma) pb0:pb7, reset (i load = 10 ma) pa0:pa5, pb4, pc0:pc7 (i load = 15 ma) pa0:pa5, pb4, pc0:pc7 v ol 0.4 0.4 1.5 v high source current total for all (6) pa0:pa5 pins and pb4 total for all (8) pc0:pc7 pins i oh 20 30 ma high sink current total for all (6) pa0:pa5 pins and pb4 total for all (8) pc0:pc7 pins i ol 40 60 ma input high voltage pa0:pa5, pb0:pb7, pc0:pc7, reset, osc1, irq/v pp v ih 0.7 x v dd v dd v input low voltage pa0:pa5, pb0:pb7, pc0:pc7, reset, osc1, irq/v pp v il v ss 0.3 x v dd v input current osc1, irq/v pp i in ? 1 a input current reset (pullup, source) reset (pulldown, sink) i in 10 ? a ma i/o ports high-z leakage current (pulldowns off) pa0:pa6, pb0:pb7, pc0:pc7 i oz ? 2 a input pulldown current pa0:pa5, pb0:pb7, pc0:pc7 (v in = v ih = 0.7 x v dd ) pa0:pa5, pb0:pb7, pc0:pc7 (v in = v il = 0.3 x v dd ) i il 40 25 100 65 280 190 a notes: 1. +4.5 v dd +5.5 v, v ss = 0 v, t l t a t h , unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. pc0:pc7 parameters only apply to mc68hc05jp6
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 195 non-disclosure agreement required 13.9 dc electrical characteristics (3.0 vdc) characteristic symbol min typ max unit output voltage i load = 10.0 a i load = ?0.0 a v ol v oh v dd ?.1 0.1 v output high voltage (i load = ?.2 ma) pb0:pb7, reset (i load = ?.0 ma) pa0:pa5, pb4, pc0:pc7 v oh v dd ?.8 v output low voltage (i load = 1.6 ma) pb0:pb7, reset (i load = 5.0 ma) pa0:pa5, pb4, pc0:pc7 v ol 0.3 0.3 v high source current total for all (6) pa0:pa5 pins and pb4 total for all (8) pc0:pc7 pins i oh 20 30 ma high sink current total for all (6) pa0:pa5 pins and pb4 total for all (8) pc0:pc7 pins i ol 40 60 ma input high voltage pa0:pa5, pb0:pb7, pc0:pc7, reset, osc1, irq/v pp v ih 0.7 x v dd ? dd v input low voltage pa0:pa5, pb0:pb7, pc0:pc7, reset, osc1, irq/v pp v il v ss 0.2 x v dd v input current osc1, irq/v pp i in ? 1 a input current reset (pullup, source) reset (pulldown, sink) i in 5 ? a ma i/o ports high-z leakage current (pulldowns off) pa0:pa6, pb0:pb7, pc0:pc7 i oz ? 2 a input pulldown current pa0:pa5, pb0:pb7, pc0:pc7 (v dd =v ih = 0.7 x v dd ) pa0:pa5, pb0:pb7, pc0:pc7 (v in = v il = 0.3 x v dd ) i il 10 4 25 20 75 40 a notes: 1. +2.7 v dd +3.3 v, v ss = 0 v, t l t a t h , unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 c only 4. pc0:pc7 parameters only apply to mc68hc05jp6
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 196 electrical specifications freescale semiconductor figure 13-1. overall internal operating frequency range versus resistance for v dd = 5 v 10%, ?0 c to 85 c figure 13-2. typical internal operating frequency range versus resistance for high v dd operating range, 25 c 0 0.50 1.00 1.50 2.00 2.50 12 k 4 7k 24 k rc oscillator resistance internal bus frequency (mhz) maximum minimum 0 0.50 1.00 1.50 2.00 2.50 12 k 47 k 24 k rc oscillator resistance internal bus frequency (mhz) v dd = 5.5 v v dd = 4.5 v
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 197 non-disclosure agreement required figure 13-3. overall internal operating frequency range versus resistance for v dd = 3 v 10%, ?0 c to 85 c figure 13-4. typical internal operating frequency range versus resistance for low v dd operating range, 25 c 12 k 47 k 24 k rc oscillator resistance internal bus frequency (mhz) maximum minimum 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 12 k 47 k 24 k rc oscillator resistance internal bus frequency (mhz) v dd = 3.3 v v dd = 2.7 v 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 198 electrical specifications freescale semiconductor 13.10 analog subsystem characteristics (5.0 vdc) characteristic symbol min max unit voltage comparators input offset voltage common-mode range comparator 1 input impedance comparator 2 input impedance direct input to comparator 2 (hold = 1, dhold = 0) divider input to comparator 2 (hold = 0, dhold = 1) v io v cmr z in z in z in 800 800 80 15 v dd ?.5 mv v k ? k ? k ? input divider ratio (comparator 2, hold = 0, dhold =1) v in = 0 to v dd ?.5 v r div 0.49 0.51 analog subsystem internal v ss offset sum of comparator offset and ir drop through v ss v aoff 20 40 mv channel selection multiplexer switch resistance r mux ?k ? external current source (pb0/an0) source current (v out = v dd /2) source current linearity (v out = 0 to v dd ?.5 vdc) discharge sink current (v out = 0.4 v) i chg i chg i dis 85 1.1 113 1 a %fs ma external capacitor (connected to pb0/an0) voltage range discharge time value of external ramping capacitor v cap t dis c ext v ss 5 v dd ?.5 10 2 v ms/ f f internal sample and hold capacitor capacitance charge/discharge time (0 to 3.5 vdc) direct connection (hold = 1, dhold = 0) divided connection (hold = 0, dhold = 1) temperature diode connection (hold = 1, dhold = 1) leakage discharge rate c sh t shchg t shdchg t shtchg c shdis 8 1 2 1 13 0.2 pf s s s v/sec internal temperature sensing diode voltage (at t j = 25 c) temperature change in voltage v d tc d 0.65 2.0 0.71 2.2 v mv/ c note: 1. +4.5 v dd +5.5 v, v ss = 0 v, t l t a t h , unless otherwise noted
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 199 non-disclosure agreement required 13.11 analog subsystem characteristics (3.0 vdc) characteristic symbol min max unit voltage comparators input offset voltage common-mode range comparator 1 input impedance comparator 2 input impedance direct input to comparator 2 (hold = 1, dhold = 0) divider input to comparator 2 (hold = 0, dhold = 1) v io v cmr z in z in z in 800 800 80 15 v dd ?.5 mv v k ? k ? k ? input divider ratio (comparator 2, hold = 0, dhold =1) v in = 0 to v dd ?.5 v r div 0.49 0.51 analog subsystem internal v ss offset v aoff 10 30 mv multiplexer switch resistance r mux ?k ? external current source (pb0/an0) source current (v out = v dd /2) source current linearity (v out = 0 to v dd ?.5 vdc) discharge sink current (v out = 0.4 v) i chg i chg i dis 75 1 104 1 a %fs ma external capacitor (connected to pb0/an0) voltage range discharge time value of external ramping capacitor v cap t dis c ext v ss 5 v dd ?.5 10 2 v ms/ f f internal sample and hold capacitor capacitance charge/discharge time (0 to 3.5 vdc) direct connection (hold = 1, dhold = 0) divided connection (hold = 0, dhold = 1) temperature diode connection (hold = 1, dhold = 1) leakage discharge rate c sh t shchg t shdchg t shtchg c shdis 8 1 2 1 13 0.1 pf s s s v/sec internal temperature sensing diode voltage (at t j = 25 c) temperature change in voltage v d tc d 0.65 2.0 0.71 2.2 v mv/ c note: 1. +2.7 v dd +3.3 v, v ss = 0 v, t l t a t h , unless otherwise noted
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 200 electrical specifications freescale semiconductor 13.12 control timing (5.0 vdc) characteristic symbol min max unit frequency of oscillation (osc) rc oscillator option crystal oscillator option external clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) f osc 0.1 dc 60 300 4.2 4.2 4.2 140 700 mhz mhz mhz khz khz internal operating frequency, crystal, or external clock (f osc /2) rc oscillator option crystal oscillator option external clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) f op 0.05 dc 30 150 2.1 2.1 2.1 70 350 mhz mhz mhz khz khz cycle time (1/f op ) external oscillator or clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) t cyc 476 14.29 2.86 33.33 6.67 ns s s 16-bit timer resolution input capture (tcap) pulse width t resl t th , t tl 4.0 284 t cyc ns interrupt pulse width low (edge-triggered) t ilih 284 ns interrupt pulse period t ilil see note 2 ? cyc osc1 pulse width (external clock input) t oh , t ol 110 ns analog subsystem response voltage comparators switching time (10-mv overdrive, either input) comparator power-up delay (bias circuit already powered up) external current source (pb0/an0) switching time (i dis to i ramp ) power-up delay (bias circuit already powered up) bias circuit power-up delay t cprop t cdelay t istart t idelay t bdelay 2 2 1 2 2 s s s s s notes: 1. +4.5 v dd +5.5 v, v ss = 0 v, t l t a t h , unless otherwise noted 2. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc .
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 201 non-disclosure agreement required 13.13 control timing (3.0 vdc) characteristic symbol min max unit frequency of oscillation (osc) rc oscillator option crystal oscillator option external clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) f osc 0.1 dc 60 300 2.1 2.1 2.1 140 700 mhz mhz mhz khz khz internal operating frequency, crystal, or external clock (f osc /2) rc oscillator option crystal oscillator option external clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) f op 0.05 dc 30 150 1.05 1.05 1.05 70 350 mhz mhz mhz khz khz cycle time (1/f op ) external oscillator or clock source internal low-power oscillator standard product (100 khz nominal) mask option (500 khz nominal) t cyc 952 14.29 2.86 33.33 6.67 ns s s 16-bit timer resolution input capture (tcap) pulse width t resl t th , t tl 4.0 284 t cyc ns interrupt pulse width low (edge-triggered) t ilih 284 ns interrupt pulse period t ilil see note 2 t cyc osc1 pulse width (external clock input) t oh , t ol 110 ns analog subsystem response voltage comparators switching time (10-mv overdrive, either input) comparator power-up delay (bias circuit already powered up) external current source (pb0/an0) switching time (i dis to i ramp ) power-up delay (bias circuit already powered up) bias circuit power-up delay t cprop t cdelay t istart t idelay t bdelay 2 2 1 2 2 s s s s s notes: 1. +2.7 v dd +3.3 v, v ss = 0 v, t l t a t h , unless otherwise noted 2. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc .
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 202 electrical specifications freescale semiconductor 13.14 siop timing (v dd = 5.0 vdc) figure 13-5. siop timing diagram characteristic symbol min typ max unit frequency of operation master slave f siop(m) f siop(s) 0.25 x f op dc 0.25 x f op 0.25 x f op 1050 khz cycle time master slave t sck(m) t sck(m) 4.0 x t cyc 4.0 x t cyc 4.0 x t cyc 3.8 s clock (sck) low time (f op = 4.2 mhz) t sckl 466 ns sdo data valid time t v 200 ns sdo hold time t ho 0ns sdi setup time t s 100 ns sdi hold time t h 100 ns note: 1. +4.5 v dd +5.5 v, v ss = 0 v, t l t a t h , unless otherwise noted t sck sck t sckl t v t ho sdo msb bit 1 lsb t h t s sdi msb lsb valid data
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 203 non-disclosure agreement required 13.15 siop timing (v dd = 3.0 vdc) characteristic symbol min typ max unit frequency of operation master slave f siop(m) f siop(s) 0.25 x f op dc 0.25 x f op 0.25 x f op 525 khz cycle time master slave t sck(m) t sck(m) 4.0 x t cyc 4.0 x t cyc 4.0 x t cyc 1.9 s clock (sck) low time (f op = 4.2 mhz) t sckl 932 ns sdo data valid time t v 400 ns sdo hold time t ho 0ns sdi setup time t s 200 ns sdi hold time t h 200 ns note: 1. +2.7 v dd +3.3 v, v ss = 0 v, t l t a t h , unless otherwise noted
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 204 electrical specifications freescale semiconductor 13.16 reset characteristics figure 13-6. stop recovery timing diagram characteristic symbol min typ max unit low-voltage reset rising recovery voltage falling reset voltage lvr hysteresis v lvrr v lvrf v lvrh 2.4 2.3 100 3.4 3.3 4.4 4.3 v v mv por recovery voltage (see note 2) v por 0 100 mv por v dd slew rate (see note 2) rising (see note 2) falling (see note 2) s vddr s vddf 0.1 0.05 v/ s reset pulse width (when bus clock active) t rl 1.5 t cyc reset pulldown pulse width (from internal reset) t rpd 3?t cyc note: 1. +2.7 v dd +5.5 v, v ss = 0 v, t l t a t h , unless otherwise noted 2. by design, not tested pch new 1ffe t rl osc1 1 reset internal clock 3 internal address bus 3 4064 or 16 t cyc 2 notes: 1. represents the internal gating of the osc1 pin 2. normal delay of 4064 t cyc or short delay option of 16 t cyc 3. internal timing signal and data information not available externally internal data bus 3 1fff new pch new pcl pcl new code op
electrical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor electrical specifications 205 non-disclosure agreement required figure 13-7. internal reset timing diagram figure 13-8. low-voltage reset timing diagram pch new 1ffe t rpd reset internal clock 3 internal address bus 3 4064 or 16 t cyc 2 notes: 1. represents the internal reset from low-voltage reset, illegal opcode fetch, or cop watchdog timeout 2. only if reset occurs during normal delay of 4064 t cyc or short delay option of 16 t cyc for initial power-up or stop recovery 3. internal timing signal and data information not available externally internal data bus 3 1fff new pch new pcl pcl new internal reset 1 pin pch new 1ffe t rpd reset internal clock 3 internal address bus 3 4064 or 16 t cyc 2 notes: 1. reset pin pulled down by internal device 2 only if lvr occurs during normal delay of 4064 t cyc or short delay option of 16 t cyc for initial power-up or stop recovery 3 internal timing signal and data information not available externally internal data bus 3 1fff new pch new pcl pcl new v dd pin 1 low voltage reset v lvrh v lvrl
non-disclosure agreement required electrical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 206 electrical specifications freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor mechanical specifications 207 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 14. mechanical specifications 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 14.3 20-pin plastic dual in-line package (case 738) . . . . . . . . . .208 14.4 20-pin small outline integrated circuit (case 751d) . . . . . . .208 14.5 28-pin plastic dual in-line package (case 710) . . . . . . . . . .209 14.6 28-pin small outline integrated circuit (case 751f) . . . . . . .209 14.2 introduction the mc68hc05jj6 is available in both a 20-pin plastic dual in-line package (pdip) and a small outline integrated circuit (soic) package. the mc68hc05jp6 is available in a 28-pin plastic dual in-line package (pdip) and a 28-pin small outline integrated circuit (soic) package. the following figure shows the latest package at the time of this publication. to make sure that you have the latest package specifications, please visit the freescale website at http://freescale.com. follow wwweb on-line instructions to retrieve the current mechanical specifications.
non-disclosure agreement required mechanical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 208 mechanical specifications freescale semiconductor 14.3 20-pin plastic dual in-line package (case 738) 14.4 20-pin small outline integrated circuit (case 751d)

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mechanical specifications mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor mechanical specifications 209 non-disclosure agreement required 14.5 28-pin plastic dual in-line package (case 710) 14.6 28-pin small outline integrated circuit (case 751f)

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non-disclosure agreement required mechanical speci?ations general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 210 mechanical specifications freescale semiconductor
mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor ordering information 211 non-disclosure agreement required general release specification mc68hc05jj6/mc68hc05jp6 section 15. ordering information 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 15.3 mc68hc05jj6 order numbers . . . . . . . . . . . . . . . . . . . . . . .212 15.4 mc68hc05jp6 order numbers . . . . . . . . . . . . . . . . . . . . . . .212 15.2 introduction this section contains instructions for ordering custom-masked rom mcus.
non-disclosure agreement required ordering information general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 212 ordering information freescale semiconductor 15.3 mc68hc05jj6 order numbers this table shows the mc order numbers for the available 20-pin package types. 15.4 mc68hc05jp6 order numbers this table shows the mc order numbers for the available 28-pin package types. package type epo oscill. type (1) 1. crystal/ceramic resonator or rc oscillator lpo freq. (khz) operating temperature range order number plastic dip (2) 2. plastic dual in-line package (p, case outline 738) xtal 100 or 500 ?0 c to 85 c mc68hc05jj6cp plastic dip xtal 100 or 500 ?0 c to 85 c mc68hc05jj6cpe (3) 3. e indicates pb free and meets rohs requirements. soic (4) 4. small outline integrated circuit package (dw, case outline 751d) xtal 100 or 500 ?0 c to 85 c mc68hc05jj6cdw soic xtal 100 or 500 ?0 c to 85 c mc68hc05jj6cdwe plastic dip rc 100 or 500 ?0 c to 85 c mc68hc05jj6cp plastic dip rc 100 or 500 ?0 c to 85 c mc68hc05jj6cpe soic rc 100 or 500 ?0 c to 85 c mc68hc05jj6cdw soic rc 100 or 500 ?0 c to 85 c mc68hc05jj6cdwe package type epo oscill. type (1) lpo freq. (khz) operating temperature range order number plastic dip (2) xtal 100 or 500 ?0 cto85 c mc68hc05jp6cp plastic dip (3) xtal 100 or 500 ?0 cto85 c mc68hc05jp6cpe (4)
ordering information mc68hc05jj6/mc68hc05jp6 rev. 3.2 general release specification freescale semiconductor ordering information 213 non-disclosure agreement required soic (5) xtal 100 or 500 ?0 cto85 c mc68hc05jp6cdw soic (6) xtal 100 or 500 ?0 cto85 c MC68HC05JP6CDWE plastic dip rc 100 or 500 ?0 cto85 c mc68hc05jp6cp plastic dip rc 100 or 500 ?0 cto85 c mc68hc05jp6cpe soic rc 100 or 500 ?0 cto85 c mc68hc05jp6cdw soic rc 100 or 500 ?0 cto85 c MC68HC05JP6CDWE 1. crystal/ceramic resonator or rc oscillator 2. plastic dual in-line package (p, case outline 710) 3. plastic dual in-line package (p, case outline 710) 4. e indicates pb free and meets rohs requirements. 5. small outline integrated circuit package (dw, case outline 751f) 6. small outline integrated circuit package (dw, case outline 751f) package type epo oscill. type (1) lpo freq. (khz) operating temperature range order number
non-disclosure agreement required ordering information general release specification mc68hc05jj6/mc68hc05jp6 rev. 3.2 214 ordering information freescale semiconductor

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